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M5M44800CJ-5

Description
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
Categorystorage    storage   
File Size141KB,21 Pages
ManufacturerMitsubishi
Websitehttp://www.mitsubishielectric.com/semiconductors/
Download Datasheet Parametric View All

M5M44800CJ-5 Overview

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

M5M44800CJ-5 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMitsubishi
Parts packaging codeSOJ
package instructionSOJ, SOJ28,.44
Contacts28
Reach Compliance Codeunknow
ECCN codeEAR99
Is SamacsysN
access modeFAST PAGE
Maximum access time50 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O typeCOMMON
JESD-30 codeR-PDSO-J28
JESD-609 codee0
length18.41 mm
memory density4194304 bi
Memory IC TypeFAST PAGE DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals28
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ28,.44
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
refresh cycle1024
Maximum seat height3.55 mm
self refreshNO
Maximum standby current0.001 A
Maximum slew rate0.09 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
Base Number Matches1

M5M44800CJ-5 Preview

M5M44800CJ,TP-5,-6,-7,
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BYBY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 4194304-BIT (524288-WORD 8-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 524288-word by 8-bit dynamic RAMs, fabricated
with the high performance CMOS process, and is ideal for large-
capacity memory systems where high speed, low power
dissipation, and low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application.
MITSUBISHI LSIs
MITSUBISHI LSIs
PIN CONFIGURATION (TOP VIEW)
(5V)V
CC
1
DQ
1
2
DQ
2
3
DQ
3
4
DQ
4
5
NC 6
W
7
9
RAS 8
A
9
28 V
SS
(0V)
27 DQ
8
26 DQ
7
25 DQ
6
24 DQ
5
23 CAS
22 OE
21 NC
20 A
8
19 A
7
18 A
6
17 A
5
16 A
4
15 V
SS
(0V)
FEATURES
Type name
M5M44800CXX-5,-5S
M5M44800CXX-6,-6S
M5M44800CXX-7,-7S
RAS
CAS Address
OE
Cycle Power
dissipa-
access access access access
time
tion
time
time
time
time
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
A
0
10
A
1
11
A
2
12
A
3
13
(5V)V
CC
14
50
60
70
13
15
20
25
30
35
13
15
20
90
110
130
450
375
325
XX=J,TP
Outline 28P0K(400mil SOJ)
Standard 28pin SOJ, 28pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS lnput level
5.5mW (Max)
CMOS Input level
550µW (Max) *
Operating power dissipation
M5M44800Cxx-5,-5S
495mW (Max)
M5M44800Cxx-6,-6S
413mW (Max)
M5M44800Cxx-7,-7S
358mW (Max)
Self refresh capability *
Self refresh current
150µA(Max)
Extended refresh capability
Extended refresh current
150µA(Max)
Fast page mode(1024-column random access),Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, CAS and OE to control output buffer impedance
1024 refresh cycles every 16.4ms (A
0
~A
9
)
1024 refresh cycles every 128ms (A
0
~A
9
) *
* :Applicable to self refresh version (M5M44800CJ,TP-5S,-6S,-7S
:option) only
(5V)V
CC
1
DQ
1
2
DQ
2
3
DQ
3
4
DQ
4
5
NC 6
W
A
9
7
9
RAS 8
A
0
10
A
1
11
A
2
12
A
3
13
(5V)V
CC
14
28 V
SS
(0V)
27 DQ
8
26 DQ
7
25 DQ
6
24 DQ
5
23 CAS
22 OE
21 NC
20 A
8
19 A
7
18 A
6
17 A
5
16 A
4
15 V
SS
(0V)
Outline 28P3Y-H(400mil TSOP Normal Bend)
APPLICATION
Microcomputer memory, Refresh memory for CRT
NC:NO CONNECTION
PIN DESCRIPTION
Pin name
A
0
~A
9
DQ
1
~DQ
8
RAS
CAS
W
OE
Vcc
Vss
Function
Address inputs
Data inputs/outputs
Row address strobe input
Column address strobe input
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
1
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
FUNCTION
In addition to normal read, write, and read-modify-write operations
the M5M44800CJ, TP provides a number of other functions, e.g.,
fast page mode, RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
RAS only refresh
Hidden refresh
CAS before RAS (Extended *) refresh
Inputs
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
CAS
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
DNC
W
NAC
ACT
ACT
ACT
DNC
DNC
DNC
DNC
DNC
OE
ACT
DNC
DNC
ACT
DNC
ACT
DNC
DNC
DNC
Row
address
Column
address
Input/Output
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC
Input
OPN
VLD
VLD
VLD
DNC
OPN
DNC
DNC
DNC
Output
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
OPN
Refresh
YES
YES
YES
YES
YES
YES
YES
YES
NO
Remark
Fast page
mode
identical
Self refresh
*
Stand-by
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : invalid, APD : applied, OPN : open
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT CAS
ROW ADDRESS RAS
STROBE INPUT
WRITE CONTROL
INPUT
W
A
0
~A
8
V
CC
(5V)
CLOCK GENERATOR
CIRCUIT
V
CC
(5V)
V
SS
(0V)
V
SS
(0V)
(8)
DATA IN
BUFFER
COLUMN DECODER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
SENSE REFRESH
AMPLIFIER & I /O CONTROL
ADDRESS INPUTS
ROW &
COLUMN
ADDRESS
BUFFER
ROW
A
0
~
A
9
DECODER
MEMORY CELL
(4194304BITS)
(8)
DATA OUT
BUFFER
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
2
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
O
P
d
T
opr
T
stg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to V
SS
Ratings
-1~7
-1~7
-1~7
50
1000
0~70
-65~150
Unit
V
V
V
mA
mW
˚C
˚C
Ta=25˚C
RECOMMENDED OPERATING CONDITIONS
(Ta=0~70˚C, unless otherwise noted)
Symbol
V
CC
V
SS
V
IH
V
IL
Parameter
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
Min
4.5
0
2.4
-0.5 * *
Limits
Nom
5.0
0
Max
5.5
0
6.0
0.8
(Note 1)
Unit
V
V
V
V
Note 1 : All voltage values are with respect to Vss.
* * : V
IL(min)
is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to V
SS
.)
ELECTRICAL CHARACTERISTICS
(Ta=0~70˚C, V
CC
=5V±10%, V
SS
=0V, unless otherwise noted)
(Note 2)
Symbol
V
OH
V
OL
I
OZ
I
I
I
CC1 (AV)
Parameter
High-level output voltage
Low-level output voltage
Off-state output current
Input current
M5M44800C-5,-5S
Average supply current
M5M44800C-6,-6S
from V
CC,
operating
(Note 3,4,5)
M5M44800C-7,-7S
Test conditions
I
OH
=-5mA
I
OL
=4.2mA
Q floating, 0V
V
OUT
5.5V
0V
V
IN
+6.0V, Other inputs pins=0V
RAS, CAS cycling
t
RC
=t
WC
=min.
output open
RAS= CAS =V
IH
, output open
RAS= CAS
V
CC
-0.5V
output open
RAS cycling, CAS= V
IH
t
RC
=min.
output open
RAS=V
IL
, CAS cycling
t
PC
=min.
output open
CAS before RAS refresh cycling
t
RC
=min.
output open
Min
2.4
0
-10
-10
Limits
Typ
I
CC2
Supply current from V
CC
, stand-by
(Note 6)
I
CC3 (AV)
M5M44800C-5,-5S
Average supply current
M5M44800C-6,-6S
from V
CC,
RAS only
refresh mode (Note 3,5)
M5M44800C-7,-7S
M5M44800C-5,-5S
Average supply current
M5M44800C-6,-6S
from V
CC,
Fast Page
(Note 3,4,5)
M5M44800C-7,-7S
Mode
M5M44800C-5,-5S
Average supply current
from V
CC
, CAS before RAS
M5M44800C-6,-6S
refresh mode
(Note 3,5)
M5M44800C-7,-7S
I
CC4(AV)
I
CC6(AV)
Max
Vcc
0.4
10
10
90
75
65
2
1.0
0.1 *
90
75
65
90
75
65
80
65
55
Unit
V
V
µA
µA
mA
mA
mA
mA
mA
I
CC8(AV)
*
Average supply current from V
CC,
Extended-Refresh mode
RAS cycling CAS
0.2V or CAS
before RAS refresh cycling
RAS
0.2V or
V
CC
-0.2V
CAS
0.2V or
V
CC
-0.2V
(Note 6)
W
0.2V or
V
CC
-0.2V
OE
0.2V or
V
CC
-0.2V
A
0
~A
9
0.2V or
V
CC
-0.2V, DQ=open
t
RC
=125µs, t
RAS
=t
RAS
min~1µs
(Note 6)
RAS=CAS
0.2V
output open
150
µA
I
CC9(AV)
*
Note
Note
Note
Note
Average supply current from V
CC,
Self-Refresh mode
150
µA
2: Current flowing into an IC is positive, out is negative.
3: I
CC1 (AV)
, I
CC3 (AV)
, I
CC4 (AV)
and I
CC6 (AV)
are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: I
CC1 (AV)
and I
CC4 (AV)
are dependent on output loading. Specified values are obtained with the output open.
5: Column address can be changed once or less while RAS=V
IL
and CAS=V
IH
3
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
CAPACITANCE
(Ta=0~70˚C, V
CC
=5V±10%, V
SS
=0V, unless otherwise noted)
Limits
Symbol
C
I (A)
C
I (CLK)
C
I / O
Parameter
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
Test conditions
V
I
=V
SS
f=1MHz
V
I
=25mVrms
Min
Typ
Max
5
7
7
Unit
pF
pF
pF
SWITCHING CHARACTERISTICS
(Ta=0~70˚C, V
CC
= 5V±10%, V
SS
=0V, unless otherwise noted, see notes 6,13,14)
Limits
Symbol
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
t
CLZ
t
OFF
t
OEZ
Parameter
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE
Output low impedance time from CAS low
Output disable time after CAS high
Output disable time after OE high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 7)
(Note 12)
(Note 12)
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
13
50
25
30
13
Min
Max
15
60
30
35
15
Min
Max
20
70
35
40
20
5
13
13
5
15
15
5
20
20
Note 6:An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 16.4ms) of RAS
inactivity before proper device operation is achieved.
Note
7:Measured with a load circuit equivalent to 2TTL loads and 100pF.
Note
8:Assumes that
t
RCD
t
RCD(max)
and
t
ASC
t
ASC(max)
.
Note
9:Assumes that
t
RCD
t
RCD(max
) and
t
RAD
t
RAD(max)
. If
t
RCD
or
t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will
increase by amount that
t
RCD
exceeds the value shown.
nOR10:Assumes
that
t
RAD
t
RAD(max)
and
t
ASC
t
ASC(max)
.
Note11:Assumes
that
t
CP
t
CP(max)
and
t
ASC
t
ASC(max)
.
Note12:
t
OFF(max)
,
t
OEZ(max)
defines the time at which the output achieves the high impedance state (I
OUT
±10µA ) and is not reference to V
OH(min)
or
V
OL(max)
.
4
M5M44800CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles)
(Ta=0~70˚C, V
CC
= 5V±10%, V
SS
=0V, unless otherwise noted, see notes 6,13,14)
Limits
Symbol
t
REF
t
REF
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
DZO
t
CDD
t
ODD
t
T
Refresh cycle time
Refresh cycle time *
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
30
18
5
0
10
13
0
0
8
13
0
0
13
13
1
Parameter
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
16.4
128
Min
Max
16.4
128
Min
Max
16.4
128
(Note 15)
37
(Note 16)
(Note 17)
25
7
Delay time, data to CAS low
Delay time, data to OE low
Delay time, CAS high to data
Delay time, OE high to data
Transition time
Note 13: The timing requirements are assumed
t
T
=5ns.
(Note 18)
(Note 18)
(Note 19)
(Note 19)
(Note 20)
50
40
20
5
0
10
15
0
0
10
15
0
0
15
15
1
45
30
10
50
50
20
5
0
10
15
0
0
10
15
0
0
20
20
1
50
35
10
50
Note
14: V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
Note
15:
t
RCD(max)
is specified as a reference point only. If
t
RCD
is less than
t
RCD(max
), access time is
t
RAC
. If
t
RCD
is greater than
t
RCD(max)
, access time is
controlled exclusively by
t
CAC
or
t
AA
.
Note
16:
t
RAD(max)
is specified as a reference point only. If
t
RAD
t
RAD(max)
and
t
ASC
t
ASC(max)
, access time is controlled exclusively by
t
AA
.
Note
17:
t
ASC(max)
is specified as a reference point only. If
t
RCD
t
RCD(max)
and
t
ASC
t
ASC(max)
, access time is controlled exclusively by
t
CAC
.
Note
18: Either
t
DZC
or
t
DZO
must be satisfied.
Note
19: Either
t
CDD
or
t
ODD
must be satisfied.
Note
20:
t
T
is measured between V
IH(min)
and V
IL(max)
.
Read and Refresh Cycles
Limits
Symbol
t
RC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
RCH
t
RRH
t
RAL
t
OCH
t
ORH
Parameter
M5M44800C-5,-5S M5M44800C-6,-6S M5M44800C-7,-7S
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read Setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
CAS hold time after OE low
RAS hold time after OE low
Note 21: Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
(Note 21)
(Note 21)
Min
90
50
13
50
13
0
0
0
25
13
13
Max
10000
10000
Min
110
60
15
60
15
0
0
0
30
15
15
Max
10000
10000
Min
130
70
20
70
20
0
0
0
35
20
20
Max
10000
10000
5
M5M44800CJ,TP-5,-5S:Under development
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