LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Choose among the following memory organizations:
IDT72V255LA
8,192 x 18
IDT72V265LA
16,384 x 18
Pin-compatible with the IDT72V275/72V285 and IDT72V295/
72V2105 SuperSync FIFOs
Functionally compatible with the 5 Volt IDT72255/72265 family
10ns read/write cycle time (6.5ns access time)
Fixed, low first word data latency time
5V input tolerant
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Retransmit operation with fixed, low first word data
latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First
Word Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and
writing simultaneously)
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
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The IDT72V255LA/72V265LA are functionally compatible versions of the
IDT72255/72265 designed to run off a 3.3V supply for very low power
consumption. The IDT72V255LA/72V265LA are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with clocked read and
write controls. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:
•
The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs, RCLK
or WCLK, is running at the higher frequency.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D
0
-D
17
LD SEN
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
WRITE CONTROL
LOGIC
RAM ARRAY
8,192 x 18
16,384 x 18
FLAG
LOGIC
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
OUTPUT REGISTER
MRS
PRS
RT
RESET
LOGIC
RCLK
REN
OE
Q
0
-Q
17
4672 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc and the SuperSyncFIFO is a trademark of Integrated Device Technology, Inc.
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