"Spansion, Inc." and "Cypress Semiconductor Corp." have merged together to deliver high-performance, high-quality solutions
at the heart of today's most advanced embedded systems, from automotive, industrial and networking platforms to highly
interactive consumer and mobile devices. The new company "Cypress Semiconductor Corp." will continue to offer "Spansion,
Inc." products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made
are the result of normal document improvements and are noted in the document history page, where supported. Future
revisions will occur when appropriate, and changes will be noted in a document history page.
Continuity of Ordering Part Numbers
Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed
in this document.
For More Information
Please contact your local sales office for additional information about Cypress products and solutions.
S25FL127S
128 Mbit (16 Mbyte)
3.0V SPI Flash Memory
Features
CMOS 3.0 Volt Core
Density
– 128 Mbits (16 Mbytes)
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Extended Addressing: 24- or 32-bit address options
– Serial Command set and footprint compatible with S25FL-A,
S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad
– AutoBoot - power up or reset and execute a Normal or Quad read
command automatically at a preselected address
– Common Flash Interface (CFI) data for configuration information.
Programming (0.8 Mbytes/s)
– 256- or 512-byte Page Programming buffer options
– Quad-Input Page Programming (QPP) for slow clock systems
Erase (0.5 Mbytes/s)
– Hybrid sector size option - physical set of sixteen 4-kbyte sectors
at top or bottom of address space with all remaining sectors of
64 kbytes
– Uniform sector option - always erase 256-kbyte blocks for software
compatibility with higher density and future devices.
Cycling Endurance
– 100,000 Program-Erase Cycles per sector minimum
Data Retention
– 20 Year Data Retention typical
Security features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against program or erase
of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or password
Cypress
®
65 nm MirrorBit Technology with Eclipse
™
Architecture
Supply Voltage: 2.7V to 3.6V
Temperature Range:
– Industrial (-40
°
C to +85
°
C)
– Industrial Plus (-40
°
C to +105
°
C)
Packages (all Pb-free)
– 8-lead SOIC (208 mil)
– 16-lead SOIC (300 mil)
– 8-contact WSON 6 x 5 mm
– BGA-24 6 x 8 mm
– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint options
– Known Good Die and Known Tested Die
Performance Summary
Maximum Read Rates
Command
Read
Fast Read
Dual Read
Quad Read
Clock Rate
(MHz)
50
108
108
108
Mbytes/s
6.25
13.5
27
54
Current Consumption
Operation
Serial Read 50 MHz
Serial Read 108 MHz
Quad Read 108 MHz
Program
Erase
Standby
kbytes/s
650
800
30
500
500
Current (mA)
16 (max)
24 (max)
47 (max)
50 (max)
50 (max)
0.07 (typ)
Typical Program and Erase Rates
Operation
Page Programming (256-byte page buffer)
Page Programming (512-byte page buffer)
4-kbyte Physical Sector Erase (Hybrid Sector
Option)
64-kbyte Physical Sector Erase (Hybrid Sector
Option)
256-kbyte Logical Sector Erase (Uniform Sector
Option)
Cypress Semiconductor Corporation
Document Number: 001-98282 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 21, 2015
S25FL127S
Contents
Features
Performance Summary
........................................................ 2
1.
1.1
1.2
1.3
1.4
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
3.
3.1
3.2
3.3
3.4
3.5
4.
4.1
4.2
4.3
4.4
5.
5.1
5.2
5.3
5.4
6.
6.1
6.2
6.3
6.4
6.5
7.
7.1
7.2
Overview
.......................................................................
General Description .......................................................
Migration Notes..............................................................
Glossary.........................................................................
Other Resources............................................................
4
4
5
7
8
7.3
7.4
7.5
7.6
8.
8.1
8.2
8.3
8.4
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
ID-CFI Address Space .................................................. 49
JEDEC JESD216B Serial Flash Discoverable
Parameters (SFDP) Space ........................................... 49
OTP Address Space ..................................................... 49
Registers....................................................................... 51
Data Protection
........................................................... 59
Secure Silicon Region (OTP)........................................ 59
Write Enable Command................................................ 59
Block Protection ............................................................ 60
Advanced Sector Protection ......................................... 61
Commands
.................................................................. 65
Command Set Summary............................................... 66
Identification Commands .............................................. 70
Register Access Commands......................................... 73
Read Memory Array Commands .................................. 82
Program Flash Array Commands ................................. 91
Erase Flash Array Commands...................................... 94
One Time Program Array Commands .......................... 99
Advanced Sector Protection Commands .................... 100
Reset Commands ....................................................... 106
Embedded Algorithm Performance Tables ................. 108
Hardware Interface
Signal Descriptions
..................................................... 9
Input/Output Summary................................................... 9
Address and Data Configuration.................................. 10
Hardware Reset (RESET#).......................................... 10
Serial Clock (SCK) ....................................................... 10
Chip Select (CS#) ........................................................ 10
Serial Input (SI) / IO0 ................................................... 11
Serial Output (SO) / IO1............................................... 11
Write Protect (WP#) / IO2 ............................................ 11
Hold (HOLD#) / IO3 / RESET# .................................... 11
Voltage Supply (V
CC
)................................................... 12
Supply and Signal Ground (V
SS
) ................................. 12
Not Connected (NC) .................................................... 12
Reserved for Future Use (RFU)................................... 12
Do Not Use (DNU) ....................................................... 13
Block Diagrams............................................................ 13
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Configuration Register Effects on the Interface ...........
Data Protection ............................................................
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Operating Ranges........................................................
Power-Up and Power-Down ........................................
DC Characteristics .......................................................
Timing Specifications
................................................
Key to Switching Waveforms .......................................
AC Test Conditions ......................................................
Reset............................................................................
AC Characteristics .......................................................
Physical Interface
......................................................
SOIC 8-Lead Package .................................................
SOIC 16-Lead Package ...............................................
WSON 6x5 Package ....................................................
FAB024 24-Ball BGA Package ....................................
FAC024 24-Ball BGA Package ....................................
15
15
15
20
25
25
26
26
26
27
29
30
30
30
31
34
38
38
40
42
44
46
10. Software Interface Reference
.................................. 109
10.1 Command Summary ................................................... 109
11.
11.1
11.2
11.3
11.4
12.
13.
14.
Serial Flash Discoverable Parameters (SFDP)
Address Map
............................................................. 110
SFDP Header Field Definitions ................................... 111
Device ID and Common Flash Interface (ID-CFI)
Address Map............................................................... 113
Registers..................................................................... 123
Initial Delivery State .................................................... 125
Ordering Information
................................................ 126
Contacting Cypress
.................................................. 126
Revision History........................................................
127
Ordering Information
Software Interface
Address Space Maps
................................................. 48
Overview ...................................................................... 48
Flash Memory Array..................................................... 48
Document Number: 001-98282 Rev. *F
Page 3 of 130
S25FL127S
1. Overview
1.1
General Description
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
The Cypress S25FL127S device is a flash non-volatile memory product using:
This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (SIngle
I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple
width interface is called SPI Multi-I/O or MIO.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to
be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase
algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates
supported, with QIO command, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous,
NOR flash memories while reducing signal count dramatically.
The S25FL127S product offers a high density coupled with the flexibility and fast performance required by a variety of embedded
applications. It is ideal for code shadowing, XIP, and data storage.
Document Number: 001-98282 Rev. *F
Page 4 of 130
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