Low Skew, 1-to-4 Multiplexed Differential/
LVCMOS-to-LVCMOS Fanout Buffer
Data Sheet
8305-02
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
General Description
The 8305-02 is a low skew, 1-to-4, Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The 8305-02 has
selectable clock inputs that accept either differential or single-ended
input levels. The clock enable is internally synchronized to eliminate
runt pulses on the outputs during asynchronous assertion/
deassertion of the clock enable pin. Outputs are forced LOW when
the clock is disabled. A separate output enable pin controls whether
the outputs are in the active or high impedance state.
Guaranteed output and part-to-part skew characteristics make the
8305-02 ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
Four LVCMOS/LVTTL outputs, (two banks of two LVCMOS
outputs)
Selectable differential CLK, nCLK pair or LVCMOS_CLK input
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 250MHz
Output skew: 100ps (maximum)
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
For functional replacement part use 8305
•
•
•
Block Diagram
OEA
CLK_EN
Pullup
Pin Assignment
OEA
OEB
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QA0
V
DDO_A
QA1
GND
QB0
V
DDO_B
QB1
GND
Pullup
D
Q
LE
LVCMOS_CLK
CLK
nCLK
CLK_SEL
Pulldown
Pulldown
Pullup
Pullup
0
0
QA0
1
1
QA1
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
8305-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
QB0
QB1
OEB
Pullup
©2016 Integrated Device Technology, Inc
1
Revision A May 19, 2016
8305-02 Data Sheet
Table 1. Pin Descriptions
Number
1
Name
OEA
Input
Type
Pullup
Description
Output enable for Bank A outputs. When LOW, QAx outputs are in HIGH
impedance state. When HIGH, QAx outputs are active. LVCMOS / LVTTL
interface levels.
Output enable for Bank B outputs. When LOW, QBx outputs are in HIGH
impedance state. When HIGH, QBx outputs are active. LVCMOS / LVTTL
interface levels.
Positive supply pins.
Pullup
Pulldown
Pullup
Pullup
Pulldown
Synchronizing clock enable. When LOW, the output clocks are disabled. When
HIGH, output clocks are enabled. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Clock select input. When HIGH, selects CLK, nCLK inputs.
When LOW, selects LVCMOS_CLK input. LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Power supply ground.
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
Output supply pin for Bank B outputs.
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
2
3
4
5
6
7
8
9, 13
10, 12
11
14, 16
15
OEB
V
DD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
GND
QB1, QB0
V
DDO_B
QA1, QA0
V
DDO_A
Input
Power
Input
Input
Input
Input
Input
Power
Output
Power
Output
Power
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
13
V
DDO_A
= V
DDO_B
= 3.3V
R
OUT
Output Impedance
V
DDO_A
= V
DDO_B
= 2.5V
V
DDO_A
= V
DDO_B
= 1.8V
V
DDO_A
= V
DDO_B
= 1.5V
9
11
15
20
Maximum
Units
pF
k
k
pF
R
PULLDOWN
Input Pulldown Resistor
C
PD
Power Dissipation Capacitance
(per output)
©2016 Integrated Device Technology, Inc
2
Revision A May 19, 2016
8305-02 Data Sheet
Function Tables
Table 3. Clock Input Function Table
Inputs
OEA, OEB
1
1
1
1 (default)
0
CLK_EN
0
0
1
1 (default)
X
CLK_SEL
0
1
0
1 (default)
X
Selected Source
LVCMOS_CLK
CLK, nCLK
LVCMOS_CLK
CLK, nCLK
Outputs
QAx, QBx
Disabled; LOW
Disabled; LOW
Enabled
Enabled
High-Impedance
NOTE: After CLK_EN switches, the clock outputs are disabled or enabled following a rising and
falling input clock edge as shown in Figure 1.
Disabled
nCLK
CLK,
LVCMOS_CLK
CLK_EN
Enabled
QA[0:1],
QB[0:1]
Figure 1. CLK_EN Timing Diagram
©2016 Integrated Device Technology, Inc
3
Revision A May 19, 2016
8305-02 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
100.3C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, V
DDO_A
= V
DDO_B
= 3.3V±5% or 2.5V±5% or 1.8V±0.15V or
1.5V±5%, T
A
= 0°C to 70°C
Symbol
V
DD
Parameter
Positive Supply Voltage
Test Conditions
Minimum
3.135
3.135
V
DDO_A,
V
DDO_B
2.375
Output Supply Voltage
1.65
1.425
I
DD
I
DDO_A
+
I
DDO_B
Power Supply Current
Output Supply Current
No Load
1.8
1.5
1.95
1.575
21
5
V
V
mA
mA
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
Units
V
V
V
©2016 Integrated Device Technology, Inc
4
Revision A May 19, 2016
8305-02 Data Sheet
Table 4B. LVCMOS DC Characteristics,
V
DD
= 3.3V±5%, V
DDO_A
= V
DDO_B
= 3.3V±5% or 2.5V±5% or 1.8V±0.15V or
1.5V±5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High
Current
Input
Low
Current
OEA, OEB,
CLK_SEL, CLK_EN
LVCMOS_CLK
OEA, OEB,
CLK_SEL, CLK_EN
LVCMOS_CLK
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DDO_X
= 3.3V ± 5%
V
OH
Output High Voltage; NOTE 1
V
DDO_X
= 2.5V ± 5%
V
DDO_X
= 1.8V ± 0.15V
V
DDO_X
= 1.5V ± 5%
V
DDO_X
= 3.3V ± 5%
V
OL
Output Low Voltage; NOTE 1
V
DDO_X
= 2.5V ± 5%
V
DDO_X
= 1.8V ± 0.15V
V
DDO_X
= 1.5V ± 5%
I
OZL
I
OZH
Output High-Impedance Low
Output High-Impedance High
-5
5
-150
-5
2.6
1.8
1.5
V
DDO_X
– 0.3
0.5
0.4
0.35
0.30
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
V
V
V
V
V
V
µA
µA
I
IL
NOTE: V
DDO_X
denotes V
DDO_A
and V
DDO_B
.
NOTE 1: Outputs terminated with 50
to V
DDO_X
/2. See Parameter Measurement Information section,
Output Load Test Circuit diagrams.
Table 4C. DC Characteristics,
V
DD
= 3.3V±5%, V
DDO_A
= V
DDO_B
= 3.3V±5% or 2.5V±5% or 1.8V±0.15V or 1.5V±5%,
T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
Input
High Current
Input
Low Current
CLK,
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
V
CMR
Peak-to-Peak Input Voltage; NOTE 1
Input Common Mode Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
©2016 Integrated Device Technology, Inc
5
Revision A May 19, 2016
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