L-ASC10
In-System Programmable
Hardware Management Expander
June 2017
Data Sheet DS1042
Features
Ten Rail Voltage Monitoring and
Measurement
• UV/OV Fault Detection Accuracy - 0.2% Typ.
• Fault Detection Speed <100 µs
• High Voltage, Single Ended and Differential
Sensing
Four Precision Trim and Margin Channels
• Closed Loop Operation
• Voltage Scaling and VID Support
Nine General Purpose Input / Output
• 5 V tolerant I/O
Two Channel Wide-Range Current
Monitoring and Measurement
• High-side current Measurement up to 12 V
• Programmable OC/UC Fault Detect
• Detects Current faults in < 1 µs
Non-Volatile Fault Logging
In-system Programmable Through I
2
C
• Non-Volatile Configuration
• Background Programming Support
System Level Support
• 3.3 V Operation, wide input supply range 2.8 V
to 3.6 V
• Industrial temperature range
• 48-pin QFN
• RoHS compliant and halogen-free
Three Temperature Monitoring and
Measurement Channels
• Programmable OT/UT Faults Threshold
• Two channels of Temperature Monitoring using
external diodes
• One On-Chip Temperature Monitor
Applications
•
•
•
•
•
Telecommunication and Networking
Industrial, Test & Measurement
Medical Systems
Servers and Storage Systems
High Reliability Systems
Four High-Side MOSFET Drivers
• Programmable Charge Pump
Application Diagram
Figure 1. Hardware Management Application Block Diagram
Hot Swap Optional
Input Rail
Up to 12 V
Rs
Vin
EN
Vout
Trim/FB
POL
Up to 10 Rails
0.6 V to 5.7 V
Current
Monitor
[1:2]
Board Temp
Transistor
Temp [1:2]
On-Die Temp
Diode
HVOUT [1:4]
GPIO
[1..9]
Trim/Margin [1:4]
Voltage
Monitor [1:10]
NV Fault
Log
On-Die
Temp
ADC
L-ASC10
Voltage, Current, Temp
(VIT) High Speed
Fault Detect/Alarms
Voltage, Current, Temp
(VIT)
Measurement and Programming
ASIC
ASC 3 Wire I/F (8 Mbps)
(WCLK, WDAT, RDAT)
ASC I/F
Fan(s)
I
2
C
CPU
Resets
FPGA: XO2 / XO3 /
ECP5 / LPTM21
VID
SPI
Memory
JTAG Programming
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
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1
DS1042_1.7
L-ASC10
In-System Programmable
Hardware Management Expander
Description
The L-ASC10 (Analog Sense and Control - 10 rail) is a
Hardware Management (Power, Thermal, and Control
Plane Management) Expander designed to be used with
Platform Manager 2, MachXO2, MachXO3, or ECP5
FPGAs to implement the Hardware Management Control
function in a circuit board. The L-ASC10 (referred to as
ASC) enables seamless scaling of power supply voltage
and current monitoring, temperature monitoring, sequence
and margin control channels. The ASC includes dedicated
interfaces supporting the exchange of monitor signal status
and output control signals with these centralized hardware
management controllers. Up to eight ASC devices can be
used to implement a hardware management system.
The ASC provides three types of analog sense channels:
voltage (nine standard channels and one high voltage chan-
nel), current (one standard voltage and one high voltage),
and temperature (two external and one internal) as shown
in Figure 2.
Each of the analog sense channels is monitored through
two independently programmable comparators to support
both high/low and in-bounds/out-of-bounds (window-com-
pare) monitor functions. The current sense channels feature
a programmable gain amplifier and a fast fault detect (<1 µs
response time) for detecting short circuit events. The tem-
perature sense channels can be configured to work with dif-
ferent external transistor or diode configurations.
Nine general purpose 5 V tolerant open-drain digital input/
output pins are provided that can be used in a system for
controlling DC-DC converters, low-drop-out regulators
(LDOs) and optocouplers, as well as for supervisory and
general purpose logic interface functions. Four high-voltage
charge pumped outputs (HVOUT1-HVOUT4) may be con-
figured as high-voltage MOSFET drivers to control high-side
MOSFET switches. These HVOUT outputs can also be pro-
grammed as static output signals or as switched outputs (to
support external charge pump implementation) operating at
a dedicated duty cycle and frequency.
The ASC device incorporates four TRIM outputs for control-
ling the output voltages of DC-DC converters. Each power
supply output voltage can be maintained typically within
0.5% tolerance across various load conditions using the
Digital Closed Loop Control mode.
The internal 10-bit A/D converter can be used to monitor the
voltage and current through the I
2
C bus. The ADC is also
used in the digital closed loop control mode of the trimming
block.
The ASC also provides the capability of logging up to 16
status records into the on-chip nonvolatile EEPROM mem-
ory. Each record includes voltage, current and temperature
monitor signals along with digital input and output levels.
The dedicated ASC Interface (ASC-I/F) is a reliable serial
channel used to communicate with a Platform Manager 2,
MachXO2, MachXO3, or ECP5 FPGA in a scalable star
topology. The centralized control algorithm in the FPGA
monitors signal status and controls output behavior via this
ASC-I/F. The ASC I
2
C interface is used by the FPGA or an
external microcontroller for ASC background programming,
interface configuration, and additional data transfer such as
parameter measurement or I/O control or status. For exam-
ple, voltage trim targets can be set over the I
2
C bus and
measured voltage, current, or temperature values can be
read over the I
2
C bus.
The ASC also includes an on-chip output control block
(OCB) which allows certain alarms and control signals a
direct connection to the GPIOs or HVOUTs, bypassing the
ASC-I/F for a faster response. The OCB is used to connect
the fast current fault detect signal to an FPGA input directly.
It also supports functions like Hot Swap with a programma-
ble hysteretic controller.
ASC Block Diagram
Figure 2. ASC Block Diagram
MOSFET &
Digital I/O Drive
Output Control
Block
ASC
Interface
(ASC-I/F)
ADC
Voltage
Sense
Non
-
Volatile
Fault Log
Temperature
Sense
Current
Sense
ADC
I
2
C
Interface
Trim & Margin
Control
2
L-ASC10
In-System Programmable
Hardware Management Expander
DC and Switching Characteristics
Absolute Maximum Ratings
Symbol
V
CCA
V
IN_VMON
V
IN_VMONGS
V
IN_HIMONP
V
IN_HIMONN
V
DIFF_HIMON
V
IN_IMONP
V
IN_IMONN
V
DIFF_IMON
V
IN_TMONP
V
IN_TMONN
V
IN_GPIO
V
OUT
Parameter
Main Power Supply
VMON input voltage
VMON input voltage ground sense
High voltage IMON input voltage
High voltage IMON return/ VMON input voltage
High voltage IMON differential voltage
Low voltage IMON1 input voltage
Low voltage IMON1 return voltage
Low voltage IMON1 differential voltage
TMON input voltage
TMON return voltage
Digital input voltage
Open-drain output voltage
HVOUT [1:4]
GPIO[1:6],
GPIO[8:10]
V
TRIM
I
SINKMAX
T
S
T
A
TRIM output voltage
Maximum Sink Current on any output
Device Storage Temperature
Ambient Temperature
–65
–40
Conditions
Min
–0.5
–0.5
–0.5
–0.5
–0.5
–2.0
–0.5
–0.5
–2.0
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
Max.
4.5
6
6
13.3
13.3
2.0
6.0
6.0
2.0
V
CCA
V
CCA
6
13.3
6
V
CCA
23
+125
+125
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
o
o
C
C
3
L-ASC10
In-System Programmable
Hardware Management Expander
Recommended Operating Conditions
Symbol
V
CCA
V
IN_VMON
V
IN_VMONGS
V
IN_HIMONP
V
IN_HIMONN
V
DIFF_HIMON
V
IN_IMONP
Parameter
Main Power Supply
1
VMON input voltage
VMON input voltage ground sense
High voltage IMON input voltage
2
High voltage IMON return/ VMON input voltage
2
High voltage IMON differential voltage
Low voltage IMON1 input voltage
Low Side Sense
Disabled
Low Side Sense
Enabled
V
IN_IMONN
Low voltage IMON1 return voltage
Low Side Sense
Disabled
Low Side Sense
Enabled
V
DIFF_IMON
V
IN_GPIO
V
OUT
Low voltage IMON1 differential voltage
Digital input voltage
Open-drain output voltage
HVOUT [1:4]
GPIO[1:6],
GPIO[8:10]
T
A
Ambient Temperature
Conditions
Min
2.8
–0.3
–0.2
4.5
4.5
0
0.6
–0.3
0.6
–0.3
0
–0.3
–0.3
–0.3
–40
Max.
3.6
5.9
0.3
13.2
13.2
500
5.9
1.0
5.9
1.0
500
5.5
13.2
5.5
+85
Units
V
V
V
V
V
mV
V
V
V
V
mV
V
V
V
o
C
1. The VCC of the I/O bank of the MachXO2, MachXO3, ECP5, or LPTM21 that is used for the ASC-I/F needs to be connected to the VCCA
of the respective ASC device. See
System Connections
section for more details
2. HIMON circuits are operational down to 3 V. Accuracy is guaranteed within Recommended Operating Conditions
Analog Specifications
Symbol
I
CCA
I
CC-HVOUT
Parameter
Supply Current
Supply Current Adder per HVOUT
Conditions
V
CCA
= 3.3 V,
Ta 25
o
C
V
HVOUT
= 12 V,
I
SRC
= 100 uA,
V
CCA
= 3.3 V,
Ta 25
o
C
V
CCA
= 3.3 V,
Ta 25
o
C
Min.
Typ.
25
Max
35
2
Units
mA
mA
I
CCPROG
Supply Current during
Programming
40
mA
ESD Performance
Please refer to the
Platform Manager 2 Product Family Qualification Summary
for complete qualification data,
including ESD performance.
4
L-ASC10
In-System Programmable
Hardware Management Expander
Power-On Reset
Symbol
T
RST
T
SAFE
T
SAFE2
T
GOOD
T
WRCLK
T
BRO
T
POR
V
TL
V
TH
V
T
C
L
Parameter
Delay from VTH to start-up state
Delay from RESETb release to ASC Safe
State Exit and I/O Release
1, 2
Delay from WRCLK start to ASC Safe State
Exit and I/O Release
1, 2, 3
Delay from I/O release to AGOOD asserted
high in FPGA section
4
Delay from RESETb release to
WRCLK start
5
Minimum duration brown out required to
trigger RESETb
Delay from Brown out to reset state
Threshold below which RESETb is LOW
Threshold above which RESETb is Hi-Z
Threshold above which RESETb is valid
Capacitive load on RESETb
2.7
0.8
200
1
56
16
1.4
5
13
2.3
1.8
Conditions
Min
Typ.
Max.
100
Units
µs
ms
µs
µs
ms
µs
µs
V
V
V
pF
1. Both T
SAFE
and T
SAFE2
must complete before I/O are released from Safe State.
2. During the calibration period before T
SAFE
and T
SAFE2
, the ASC may ignore RESETb being driven low. After T
SAFE
and T
SAFE2
, the ASC
can be reset by another device by driving RESETb low.
3. Safe State is released at ASC after a fixed number (64) of WRCLK cycles (typ. 8 MHz frequency) and three ASC-I/F data packets are prop-
erly detected.
4. AGOOD asserted in the FPGA on the next ASC-I/F packet after I/O exits Safe State as ASC.
5. Parameter is dependent on the FPGA configuration refresh time during POR. See Platform Manager 2, MachXO2, MachXO3, or ECP5 data
sheet for details.
Figure 3. ASC Power-On Reset
V
TH
V
TL
V
T
T
BRO
V
CCA
T
RST
T
POR
RESETb
T
SAFE2
T
SAFE
I/O
Release
T
GOOD
AGOOD
T
WRCLK
WRCLK
Power On Reset - Startup
Brownout Behavior
5
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