MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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DSP56307DS/D
Rev. 0, 8/10/98
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24-BIT DIGITAL SIGNAL PROCESSOR
DSP56307
The Motorola DSP56307, a member of the DSP56300 family of programmable digital signal
processors (DSPs), supports wireless infrastructure applications with general filtering
operations. The on-chip enhanced filter coprocessor (EFCOP) processes filter algorithms in
parallel with core operation, thus increasing overall DSP performance and efficiency. Like the
other family members, the DSP56307 uses a high-performance, single-clock-cycle-per-instruction
engine (code-compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit
addressing, an instruction cache, and a direct memory access controller, as in
Figure 1
. The
DSP56307 offers performance at 100 million instructions (MIPS) per second using an internal
100 MHz clock with a 2.5 volt core and independent 3.3 volt input/output power.
3
16
6
6
Memory Expansion Area
Enhanced
Filtering
Co-
processor
EFCOP
Program
RAM
16 K
×
24 or
(Program
RAM
15 K
×
24 and
Instruction
Cache
1024
×
24)
PM_EB
SCI
Interface
Triple
Timer
Host
Interface
HI08
ESSI
Interface
X Data
RAM
24 K
×
24
Y Data
RAM
24 K
×
24
PIO_EB
XM_EB
Address
Generation
Unit
Six Channel
DMA Unit
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
External
Bus
18
Address
Bootstrap
ROM
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Interface
and
13
Control
I - Cache
Control
External
Data Bus
Switch
Internal
Data
Bus
Switch
24
Data
Power
Mngmnt.
Clock
Generator
PLL
Program
Interrupt
Controller
2
Program
Decode
Controller
MODA/
IRQA
MODB/
IRQB
MODC/
IRQC
MODD/
IRQD
Program
Address
Generator
Data ALU
24
×
24+56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
5
JTAG
OnCE™
EXTAL
XTAL
DE
RESET
PINIT/
NMI
AA1367
Figure 1
DSP56307 Block Diagram
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without
notification.
©1998 MOTOROLA, INC.
TABLE OF CONTENTS
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SECTION 5
APPENDIX A
SIGNALS/CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . A-1
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Index-1
FOR TECHNICAL ASSISTANCE:
Telephone:
Email:
Internet:
1-800-521-6274
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
Data Sheet Conventions
OVERBAR
ÒassertedÓ
ÒdeassertedÓ
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)
Means that a high true (active high) signal is high or that a low true (active low)
signal is low
Means that a high true (active high) signal is low or that a low true (active low)
signal is high
Signal/Symbol
PIN
PIN
PIN
PIN
Note:
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage
*
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
*Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
ii
DSP56307 Technical Data
MOTOROLA
DSP56307
Features
FEATURES
High-Performance DSP56300 Core
¥
¥
¥
¥
100 million instructions per second (MIPS) with a 100 MHz clock at 2.5 V core and
3.3 V I/O
Object code compatible with the DSP56000 core
Highly parallel instruction set
Data arithmetic logic unit (ALU)
Ð
Ð
Ð
Ð
¥
Fully pipelined 24 x 24-bit parallel multiplier-accumulator
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
Conditional ALU instructions
24-bit or 16-bit arithmetic support under software control
Program control unit (PCU)
Ð
Ð
Ð
Ð
Ð
Ð
Position independent code (PIC) support
Addressing modes optimized for DSP applications (including immediate offsets)
On-chip instruction cache controller
On-chip memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
¥
Direct memory access (DMA)
Ð
Ð
Ð
Ð
Six DMA channels supporting internal and external accesses
One-, two-, and three- dimensional transfers (including circular buffering)
End-of-block-transfer interrupts
Triggering from interrupt lines and all peripherals
¥
Phase-locked loop (PLL)
Ð
Ð
Allows change of low power divide factor (DF) without loss of lock
Output clock with skew elimination
On-Chip Emulation (OnCE
™
) module
Joint test action group (JTAG) test access port (TAP)
Address trace mode reflects internal Program RAM accesses at the external port
¥
Hardware debugging support
Ð
Ð
Ð
MOTOROLA
DSP56307 Technical Data
iii
DSP56307
Features
Enhanced Filtering Coprocessor (EFCOP)
The on-chip filtering and echo-cancellation coprocessor runs in parallel to the DSP core.
On-Chip Memories
¥
¥
64 K on-chip RAM total
Program RAM, Instruction Cache, X data RAM, and Y data RAM size is programmable:
Instruction
Cache Size
X Data RAM
Size*
Y Data RAM
Size*
Instruction
Cache
Switch
Mode
MSW1 MSW0
0/1
0/1
0
0
0
0
1
1
1
1
0/1
0/1
0
0
1
1
0
0
1
1
Program RAM
Size
16K
×
24-bit
0
24K
×
24-bit
24K
×
24-bit
disabled disabled
1 K
×
24-bit
1024
×
24-bit
24K
×
24-bit
24K
×
24-bit
enabled
disabled
48K
×
24-bit
0
8K
×
24-bit
8K
×
24-bit
disabled
enabled
47K
×
24-bit
1024
×
24-bit
8K
×
24-bit
8K
×
24-bit
enabled
enabled
40K
×
24-bit
0
12K
×
24-bit
12K
×
24-bit
disabled
enabled
39K
×
24-bit
1024
×
24-bit
12K
×
24-bit
12K
×
24-bit
enabled
enabled
32K
×
24-bit
0
16K
×
24-bit
16K
×
24-bit
disabled
enabled
31K
×
24-bit
1024
×
24-bit
16K
×
24-bit
16K
×
24-bit
enabled
enabled
24K
×
24-bit
0
20K
×
24-bit
20K
×
24-bit
disabled
enabled
23K
×
24-bit
1024
×
24-bit
20K
×
24-bit
20K
×
24-bit
enabled
enabled
*Includes 4K
×
24-bit shared memory (i.e., memory shared by the core and the EFCOP)
¥
192 x 24-bit bootstrap ROM
Off-Chip Memory Expansion
¥
¥
¥
¥
¥
Data memory expansion to two 256K
×
24-bit word memory spaces (or up to two
4 M
×
24-bit word memory spaces by using the address attribute AA0ÐAA3 signals)
Program memory expansion to one 256K
×
24-bit words memory space (or up to one
4 M
×
24-bit word memory space by using the address attribute AA0ÐAA3 signals)
External memory expansion port
Chip Select Logic for glueless interface to static random access memory (SRAMs)
On-chip DRAM Controller for glueless interface to dynamic random access memory
(DRAMs)
iv
DSP56307 Technical Data
MOTOROLA
DSP56307
Target Applications
On-Chip Peripherals
¥
Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses
(e.g., ISA) and provides glueless connection to a number of industry-standard
microcomputers, microprocessors, and DSPs
Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three
transmitters (allows six-channel home theater)
Serial communications interface (SCI) with baud rate generator
Triple timer module
Up to 34 programmable general purpose input/output (GPIO) pins, depending on which
peripherals are enabled
¥
¥
¥
¥
Reduced Power Dissipation
¥
¥
¥
¥
Very low power CMOS design
Wait and Stop low-power standby modes
Fully static logic, operation frequency down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent,
and mode-dependent)
TARGET APPLICATIONS
The DSP56307 is intended for applications requiring a large amount of on-chip memory, such as
wireless infrastructure applications. The EFCOP may be used to accelerate general filtering
applications, such as echo-cancellation applications, correlation, and general purpose
convolution-based algorithms.
MOTOROLA
DSP56307 Technical Data
v
Power technology
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