A5191HRT
HART Modem
Description
The A5191HRT is a single−chip, CMOS modem for use in highway
addressable remote transducer (HART) field instruments and masters.
The modem and a few external passive components provide all of the
functions needed to satisfy HART physical layer requirements
including modulation, demodulation, receive filtering, carrier detect,
and transmit−signal shaping.
The A5191HRT uses phase continuous frequency shift keying
(FSK) at 1200 bits per second. To conserve power the receive circuits
are disabled during transmit operations and vice versa. This provides
the half−duplex operation used in HART communications.
Features
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Single−chip, Half−duplex 1200 Bits per Second FSK Modem
Bell 202 Shift Frequencies of 1200 Hz and 2200 Hz
3.0 V − 5.5 V Power Supply
Transmit−signal Wave Shaping
Receive Band−pass Filter
Low Power: Optimal for Intrinsically Safe Applications
Compatible with 3.3 V or 5 V Microcontroller
Internal Oscillator Requires 460.8 kHz Crystal or Ceramic Resonator
Meets HART Physical Layer Requirements
Industrial Temperature Range of −40°C to +85°C
Available in 28−pin PLCC, 32−pin QFN and 32−pin LQFP Packages
These are Pb−Free Devices
PLCC−28
P SUFFIX
CASE 776AA
QFN−32
N SUFFIX
CASE 488AM
LQFP−32
L SUFFIX
CASE 561AB
MARKING DIAGRAMS
(Top Views)
1 28
A5191HRTPG
AWLYYWW
Applications
•
HART Multiplexers
•
HART Modem Interfaces
•
4 − 20 mA Loop Powered Transmitters
A5191
HRTL
AWLYYWWG
32
1
1
A5191
HRTNG
AWLYYWW
G
A5191HRTxx = Specific Device Code
xx
= P (PLCC), L (LQFP) or N (QFN)
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
September, 2016 − Rev. 9
Publication Order Number:
A5191HRT/D
A5191HRT
BLOCK DIAGRAM
VDD
VDDA
RxAFI
RxAF
RESET
Demodulator
Logic
Rx Comp
Rx HP Filter
RxA
FSK_IN
RxD
Carrier Detect
Counter
Carrier Comp
AREF
CD
CDREF
DEMODULATOR
TxD
Numeric
Controlled
Oscillator
Sine
Shaper
TxA
FSK_OUT
RTS
Crystal
Oscillator
BIAS
MODULATOR
A5191HRT
VSS
VSSA
XOUT XIN
CBIAS
Figure 1. Block Diagram A5191HRT
ELECTRICAL SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
Symbol
T
A
T
S
T
J
V
DD
V
IN
, V
OUT
Ambient
Storage Temperature
Junction Temperature
Supply Voltage
DC Input, Output
Parameter
Min
−40
−55
−40
−0.3
−0.3
Max
+85
150
150
6.0
VDD + 0.3
Units
°C
°C
°C
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. CMOS devices are damaged by high−energy electrostatic discharge. Devices must be stored in conductive foam or with all pins shunted.
Precautions should be taken to avoid application of voltages higher than the maximum rating. Stresses above absolute maximum ratings
may result in damage to the device.
2. Remove power before insertion or removal of this device.
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A5191HRT
Table 2. DC CHARACTERISTICS
(V
DD
= 3.0 V to 5.5 V, V
SS
= 0 V, T
A
= −40°C to +85°C)
Symbol
V
IL
V
IH
V
OL
V
OH
C
IN
Input Voltage, Low
Input Voltage, High
Output Voltage, Low (I
OL
= 0.67 mA)
Output Voltage, High (I
OH
= −0.67 mA)
Input Capacitance of:
Analog Input
RXA
Digital Input
Input Leakage Current
Output Leakage Current
Power Supply Current
(RBIAS = 500 kW, AREF = 1.235 V)
Dynamic Digital Current
Analog Reference
Carrier Detect Reference (AREF – 0.08 V)
Comparator Bias Current
(RBIAS = 500 kW, AREF = 1.235 V)
3.3 V
5.0 V
5.0 V
3.3 V
5.0 V
3.3 V
5.0 V
150
150
25
1.2
1.235
2.5
1.15
2.42
2.5
330
300
Parameter
V
DD
3.0 – 5.5 V
3.0 – 5.5 V
3.0 – 5.5 V
3.0 – 5.5 V
2.4
2.9
25
3.5
±500
±10
450
600
200
2.6
0.7 * V
DD
0.4
Min
Typ
Max
0.3 * V
DD
Units
V
V
V
V
pF
pF
pF
nA
mA
mA
mA
mA
V
V
V
mA
I
IL
/I
IH
I
OLL
I
DDA
I
DDD
A
REF
CD
REF
(Note 3)
C
BIAS
3. The HART specification requires carrier detect (CD) to be active between 80 and 120 mVp−p. Setting CDREF at AREF − 0.08 VDC will set
the carrier detect to a nominal 100 mVp−p.
Table 3. AC CHARACTERISTICS
(V
DD
= 3.0 V to 5.5 V, V
SS
= 0 V, T
A
= −40°C to +85°C) (Note 4)
Pin Name
RxA
Description
Receive analog input
Leakage current
Frequency – mark (logic 1)
Frequency – space (logic 0)
Output of the high−pass filter
Slew rate
Gain bandwidth (GBW)
Voltage range
Carrier detect and receive filter input
Leakage current
Modulator output
Frequency – mark (logic 1)
Frequency – space (logic 0)
Amplitude (AREF 1.235 V)
Slew Rate − mark (logic 1)
Slew Rate − space (logic 0)
Loading (AREF = 1.235 V)
Receive digital output
Rise/fall time
Carrier detect output
Rise/fall time
1196.9
2194.3
500
1860
3300
30
20
ns
20
Min
Typ
Max
±150
1210
2220
Units
nA
Hz
Hz
V/ms
kHz
V
nA
Hz
Hz
mV
V/s
V/s
kW
ns
1190
2180
1200
2200
0.025
RxAF
150
0.15
V
DD
– 0.15
±500
RxAFI
TxA
RxD
CD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. The modular output frequencies are proportional to the input clock frequency (460.8 kHz).
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A5191HRT
Table 4. MODEM CHARACTERISTICS
(V
DD
= 3.0 V to 5.5 V, V
SS
= 0 V, T
A
= −40°C to +85°C)
Parameter
Demodulator jitter
Conditions
1. Input frequencies at 1200 Hz
±
10 Hz, 2200 Hz
±
20 Hz
2. Clock frequency of 460.8 kHz
±
0.1%
3. Input (RxA) asymmetry, 0
Min
Typ
Max
12
Units
% of 1 bit
Table 5. CERAMIC RESONATOR − External Clock Specifications
(V
DD
= 3.0 V to 5.5 V, V
SS
= 0 V, T
A
= −40°C to +85°C)
Parameter
Resonator
Tolerance
Frequency
External
Clock frequency
Duty cycle
Amplitude
456.2
40
Min
Typ
Max
1.0
460.8
460.8
50
V
OH
− V
OL
465.4
60
Units
%
kHz
kHz
%
V
TYPICAL APPLICATION
POWER
3.0 to 5.5 V
VDD
RESET
VDDA
RxAFI
RxAF
RxA
NCP301
RxD
AREF
CD
VDDA
A5191HRT
LM285
HART IN
CDREF
mC
TxD
RTS
TxA
S
4 – 20 mA
DAC OUT
HART &
4 – 20 mA OUT
XOUT
460.8 kHz
XIN
CBIAS
VSS
VSSA
Figure 2. Application Diagram A5191HRT
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A5191HRT
TEST3
TEST12
TEST4
TEST2
TEST1
RxD
26
4
3
2
1
28
TEST5
RESET
TEST7
TEST8
TEST9
TxA
AREF
5
6
7
8
9
10
11
CD
27
25
24
23
TEST11
TxD
RTS
VDD
VSS
XIN
XOUT
A5191HRT
22
21
20
19
12
13
14
15
16
17
18
TEST10
CDREF
CBIAS
Figure 3. Pin Out A5191HRT in 28-pin PLCC
Table 6. PIN OUT SUMMARY 28−PIN PLCC
Pin No.
1
2, 3, 4
5
6
7, 8, 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Signal Name
TEST1
TEST2, 3, 4
TEST5
RESETB
TEST7, 8, 9
TxA
AREF
CDREF
CBIAS
TEST10
VDDA
RxA
RxAF
RxAFI
XOUT
XIN
VSS
VDD
RTSB
TxD
TEST11
RxD
CD
TEST12
Type
Input
−
Input
Input
Input
Output
Input
Input
Output
Input
Power
Input
Output
Input
Output
Input
Ground
Power
Input
Input
−
Output
Output
−
Connect to VSS
Do Not Connect
Connect to VSS
Reset all digital logic when low
Connect to VSS
Transmit Data Modulator output
Analog reference voltage
Carrier detect reference voltage
Comparator bias current
Connect to VSS
Analog supply voltage
Receive Data Modulator input
Analog receive filter output
Analog receive comparator input
Crystal oscillator output
Crystal oscillator input
Ground
Digital supply voltage
Request to send
Input transmit date, transmitted HART data stream from microcontroller
Do Not Connect
Received demodulated HART data to microcontroller
Carrier detect output
Do Not Connect
Pin Description
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5
VDDA
RxAFI
RxAF
RxA
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