841N254BKILFT datasheet, PDF - EEWORLD Datasheet

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841N254BKILFT: DescriptionVFQFPN-32, Reel; CategoryThe embedded processor and controller Microcontrollers and processors; File Size771KB，26 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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841N254BKILFT Overview

VFQFPN-32, Reel

841N254BKILFT Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	VFQFPN
package instruction	HVQCCN,
Contacts	32
Manufacturer packaging code	NLG32P1
Reach Compliance Code	compli
ECCN code	EAR99
Other features	ALSO OPERATES AT 3.3 V SUPPLY
JESD-30 code	S-XQCC-N32
JESD-609 code	e3
length	5 mm
Humidity sensitivity level	3
Number of terminals	32
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	250 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	25 MHz
Maximum seat height	1 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

841N254BKILFT Preview

FemtoClock

NG Crystal-to-LVDS/

HCSL Clock Synthesizer

841N254B

Datasheet

Description

The 841N254B is a 4-output clock synthesizer designed for S-RIO

1.3 and 2.0 reference clock applications. The device generates

four copies of a selectable 250MHz, 156.25MHz, 125MHz or

100MHz clock signal with excellent phase jitter performance. The

four outputs are organized in two banks of two LVDS and two

HCSL ouputs. The device uses IDT’s fourth generation

FemtoClock

NG technology for an optimum of high clock

frequency and low phase noise performance, combined with a low

power consumption and high power supply noise rejection. The

synthesized clock frequency and the phase-noise performance

are optimized for driving RIO 1.3 and 2.0 SerDes reference

clocks.

The device supports 3.3V and 2.5V voltage supplies and is

packaged in a small 32-lead VFQFN package. The extended

temperature range supports wireless infrastructure,

telecommunication and networking end equipment requirements.

Features

▪

Fourth generation FemtoClock

(NG) technology

▪

Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output

▪

clock synthesized from a 25MHz fundamental mode crystal

Four differential clock outputs (two LVDS and two HCSL

outputs)

Crystal interface designed for 25MHz,

parallel resonant crystal

RMS phase jitter at 156.25MHz, using a 25MHz crystal

(1MHz - 20MHz): 0.27ps (typical)

RMS phase jitter at 156.25MHz, using a 25MHz crystal

(12kHz - 20MHz): 0.32ps (typical)

Power supply noise rejection PSNR: -50dB (typical)

LVCMOS interface levels for the frequency select input

Full 3.3V or 2.5V supply voltage

Lead-free (RoHS 6) packaging

-40°C to 85°C ambient operating temperature

Function Table

Inputs

F_SEL1

0 (default)

F_SEL0

0 (default)

Output Frequency with

XTAL

= 25MHz

156.25MHz

125MHz

100MHz

250MHz

NOTE: F_SEL[1:0] are asynchronous controls.

Block Diagram

April 17, 2018

841N254B Datasheet

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin Description and Pin Characteristic Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Function Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Typical Phase Noise at 156.25MHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Recommendations for Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Interface to IDT S-RIO Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Overdriving the XTAL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

HCSL Recommended Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

LVDS Driver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

VFQFN EPAD Thermal Release Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Schematic Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Reliability Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

April 17, 2018

841N254B Datasheet

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

1, 8, 13, 32

2, 4

5, 17,

23, 25, 31

11,

15,

18, 19

21, 22

26, 27

29, 30

Name

DDA

GND

REF_CLK

nOEA

nOEB

REF_SEL

XTAL_IN,

XTAL_OUT

BYPASS

F_SEL0,

F_SEL1

QA1, nQA1

DDOA

QA0, nQA0

IREF

nQB1, QB1

DDOB

nQB0, QB0

Power

Type

[a]

Core supply pins.

No connect.

Analog power supply.

Power supply ground.

Pulldown

Description

Unused

Power

Input

Output

Power

Output

Input

Output

Power

Output

Pulldown

Alternative single-ended reference clock input. LVCMOS/LVTTL interface levels.

Output enable input. See

Table 6

for function. LVCMOS/LVTTL interface levels.

Output enable input. See

Table 7

for function. LVCMOS/LVTTL interface levels.

Reference select input. See

Table 4

for function.

LVCMOS/LVTTL interface levels.

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

Bypass mode select pin. See

Table 5

for function.

LVCMOS/LVTTL interface levels.

Frequency select pin. See

Table 3

for function. LVCMOS/LVTTL interface levels.

Differential clock output. LVDS interface levels.

Output supply pin for QAx outputs.

Differential clock output. LVDS interface levels.

External fixed precision resistor (475) from this pin to ground provides a

reference current used for differential current-mode QBx, nQBx clock outputs.

Differential clock output. HCSL interface levels.

Output supply pin for QBx outputs.

Differential clock output. HCSL interface levels.

[a]

Pulldown

refers to internal input resistors. See

Table 2

for typical values.

Table 2. Pin Characteristics

Symbol

PULLDOWN

Parameter

Input Capacitance

Input Pulldown Resistor

Test Conditions

Minimum

Typical

100

Maximum

Units

k

April 17, 2018

841N254B Datasheet

Function Tables

Table 3. Output Divider and Output Frequency

Inputs

[a]

F_SEL1

0 (default)

F_SEL0

0 (default)

Operation

OUT

= f

REF

* 25 ÷ 4

OUT

= f

REF

* 5

OUT

= f

REF

* 4

OUT

= f

REF

* 10

OUT

with f

REF

= 25MHz

156.25MHz

125MHz

100MHz

250MHz

[a] F_SEL[1:0] are asynchronous controls.

Table 4. PLL Reference Clock Select Function Table

Input

REF_SEL

[a]

0 (default)

Operation

The crystal interface is selected as reference clock

The REF_CLK input is selected as reference clock

[a] REF_SEL is an asynchronous control.

Table 5. PLL BYPASS Function Table

Input

BYPASS

[a]

0 (default)

Operation

PLL is enabled. The reference frequency f

REF

is multiplied by the PLL

feedback divider of 25 and then divided by the selected output divider N.

PLL is bypassed. The reference frequency f

REF

is divided by the selected

output divider N. AC specifications do not apply in PLL bypass mode.

[a] BYPASS is an asynchronous control.

Table 6. nOEA Output Enable Function Table

Input

nOEA

[a]

0 (default)

Operation

QA0, nQA0 and QA1, nQA1 outputs are enabled

QA0, nQA0 and QA1, nQA1 outputs are disabled (high-impedance)

[a] nOEA is an asynchronous control.

April 17, 2018

841N254B Datasheet

Table 7. nOEB Output Enable Function Table

Input

nOEB

[a]

0 (default)

Operation

QB0, nQB0 and QB1, nQB1 outputs are enabled

QB0, nQB0 and QB1, nQB1 outputs are disabled (high-impedance)

[a] nOEB is an asynchronous control.

Absolute Maximum Ratings

Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the

DC Characteristics

or AC Characteristics

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Table 8. Absolute Maximum Ratings

Item

Supply Voltage, V

Inputs, V

XTAL_IN

Other Inputs

Outputs, V

(HCSL)

Outputs, I

(LVDS)

Continuous Current

Surge Current

Package Thermal Impedance,



Storage Temperature, T

STG

Rating

3.6V

0V to 2V

-0.5V to V

+ 0.5V

-0.5V to V

+ 0.5V

10mA

15mA

37.7°C/W (0 mps)

-65C to 150C

April 17, 2018

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841N254BKILFT Related Products

	841N254BKILFT	841N254BKILF	841N254AKILFT
Description	VFQFPN-32, Reel	VFQFPN-32, Tray	VFQFPN-32, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to
Parts packaging code	VFQFPN	VFQFPN	VFQFPN
package instruction	HVQCCN,	HVQCCN,	5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
Contacts	32	32	32
Manufacturer packaging code	NLG32P1	NLG32P1	NLG32P1
Reach Compliance Code	compli	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
Other features	ALSO OPERATES AT 3.3 V SUPPLY	ALSO OPERATES AT 3.3 V SUPPLY	IT CAN ALSO OPERATES WITH 3.3V SUPPLY
JESD-30 code	S-XQCC-N32	S-XQCC-N32	S-XQCC-N32
JESD-609 code	e3	e3	e3
length	5 mm	5 mm	5 mm
Humidity sensitivity level	3	3	3
Number of terminals	32	32	32
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Maximum output clock frequency	250 MHz	250 MHz	250 MHz
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260	260
Master clock/crystal nominal frequency	25 MHz	25 MHz	25 MHz
Maximum seat height	1 mm	1 mm	1 mm
Maximum supply voltage	2.625 V	2.625 V	2.625 V
Minimum supply voltage	2.375 V	2.375 V	2.375 V
Nominal supply voltage	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn) - annealed
Terminal form	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	5 mm	5 mm	5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER
Base Number Matches	1	1	-
Maker	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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