SY89113U
2.5V Low Jitter, Low Skew 1:12 LVDS Fanout
Buffer with 2:1 Input MUX and Internal Termination
General Description
The SY89113U is a 2.5V low jitter, low skew, 1:12
LVDS fanout buffer optimized for precision telecom
and enterprise server distribution applications. The
input includes a 2:1 MUX for clock switchover
applications. Unlike other multiplexers, this input
includes a unique isolation design that minimizes
channel-to-channel
crosstalk.
The
SY89113U
distributes clock frequencies from DC to >1GHz
guaranteed over temperature and voltage. The
SY89113U incorporates a synchronous output enable
(EN) so that the outputs will only be enabled/disabled
when they are already in the LOW state.
CLK0 differential input includes Micrel's unique, 3-pin
input termination architecture that directly interfaces to
any differential signal (AC- or DC-coupled) as small as
100mV (200mV
PP
) without any level shifting or
termination resistor networks in the signal path.
CLK1 differential input includes a new version of
Micrel's unique, Any-Input architecture that directly
interfaces with single-ended TTL/CMOS logic
(including 3.3V logic), single-ended LVPECL,
differential (AC- or DC-coupled) LVDS, HSTL, CML,
and LVPECL logic levels as small as 200mV
(400mV
PP
). CLK1 input requires external termination.
LVDS output swing 325mV into 100Ω with extremely
fast rise/fall time guaranteed to be less than 250ps.
The SY89113U operates from a 2.5V±5% supply and
is guaranteed over the full industrial temperature
range of -40°C to +85°C. The SY89113U is part of
Micrel's high-speed, Precision Edge
®
product line.
All support documentation can be found on Micrel’s
web site at:
www.micrel.com.
Precision Edge
®
Features
•
Selects between 1 of 2 inputs, and provides 12
precision, low skew LVDS output copies
•
Guaranteed AC performance over temperature and
voltage:
– DC to >1GHz throughput
– <975ps propagation delay CLK0-to-Q
– <250ps rise/fall time
– <25ps output-to-output skew
•
Ultra-low jitter design:
– <1ps
RMS
random jitter
– <10ps
PP
total jitter (clock)
– <1ps
RMS
cycle-to-cycle jitter
– <0.7ps
RMS
crosstalk induced jitter
•
Unique, patent-pending 2:1 input MUX provides
superior isolation to minimize channel-to-channel
crosstalk
•
CLK0 input features a unique, patent-pending input
termination and VT pin that accepts AC- and DC-
coupled inputs (CML, LVPECL, LVDS)
•
CLK1 accepts virtually any logic standard:
– Single-ended: TTL/CMOS (including 3.3V logic),
LVPECL
– Differential: LVPECL, LVDS, CML, HSTL
•
325mV LVDS-compatible output swing
•
Power supply: 2.5V +5%
•
Industrial temperature range –40°C to +85°C
•
Available in 44-pin (7mm x 7mm) MLF™ package
Applications
•
•
•
•
Precision Edge is a registered trademark of Micrel, Inc.
MLF and
MicroLeadFrame
are trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Multi-processor server
SONET/SDH clock/data distribution
Fibre Channel distribution
Gigabit Ethernet clock distribution
March 2005
M9999-032905
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89113U
Functional Block Diagram
March 2005
2
M9999-032905
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89113U
Ordering Information
(1)
Part Number
SY89113UMG
SY89113UMGTR
(2)
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
Package Type
MLF-44
MLF-44
Operating
Range
Industrial
Industrial
Package Marking
SY89113U with Pb-Free bar-line indicator
SY89113U with Pb-Free bar-line indicator
Lead
Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
44-Pin MLF
TM
(MLF-44)
Truth Table
EN
H
H
L
Note:
1. Transition occurs on next negative transition of the non-inverted input.
CLK_SEL
L
H
X
Q
CLK0
CLK1
L
(1)
/Q
/CLK0
/CLK1
H
(1)
March 2005
3
M9999-032905
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89113U
Pin Description
Pin Number
1, 6, 11, 22, 34
Pin Name
GND,
Exposed Pad
CLK0, /CLK0
Pin Function
Ground. GND pins and exposed pad must both be connected to the most negative
potential of chip the ground.
Differential Inputs: This input pair is a differential signal input to the device. Input
accepts AC- or DC-coupled signals as small as 100mV (200mV
PP
). Each pin of the
pair internally terminates to a VT pin through 50Ω. Note that this input defaults to an
indeterminate state if left open. Please refer to the "CLK0 Input Interface
Applications" section for more details.
Input Termination Center-Tap: Each side of the differential input pair CLK0, /CLK0
terminates to the VT pin. The VT pin provides a center-tap to a termination network
for maximum interface flexibility. See “CLK0 Input Interface Applications” section for
more details. For DC-coupled CML or LVDS inputs, the VT pin is left floating.
Reference Voltage: This output biases to V
CC
–1.2V. It is used when AC-coupling the
input CLK0. For AC-coupled applications, connect VREF-AC0 to the VT0 pin and
bypass with 0.01µF low ESR capacitor to V
CC
. See “CLK0 Input Interface
Applications” section for more details. Maximum sink/source current is ±1.5mA. Due
to the limited drive capability, the VREF-AC0 pin is only intended to drive its
respective input pin.
Input Termination Pin: When CLK1 is driven by a single-ended TTL/CMOS signal, tie
this pin to GND. In all other modes, let this pin float. See “CLK1 Interface
Applications” section for more details.
Differential Inputs: This input pair is a differential signal input to the device. This input
accepts Any-Logic standard as small as 200mV (400mV
PP
). Note that this input
defaults to an indeterminate state if left open. Tie either the true or the complement
input to ground while the other input is floating. This input can be used for single-
ended signals (including TTL/CMOS signals from a 3.3V driver). See “CLK1 Input
Interface Applications” section for more details.
Reference Voltage: This output biases to V
CC
–1.425V. VBB1 is designed to act as a
switching reference for the CLK1 and /CLK1 inputs when configured in single-ended
PECL input mode. VBB1 can be used for AC-coupling of CLK1, see Figure 4d for
details. Maximum sink/source current is ±1.5mA. Due to the limited drive capability,
the VBB1 pin is only intended to drive its respective input pin.
This single-ended, TTL/CMOS-compatible input functions as a synchronous output
enable. The synchronous enable ensures that enable/disable will only occur when
the outputs are in a logic LOW state. Note that this input is internally connected to a
25kΩ pull-up resistor and will default to logic HIGH state (enable) if left open.
Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors and place as
close to the VCC pins as possible.
This single-ended, TTL/CMOS-compatible input selects the inputs to the multiplexer.
Note that this input is internally connected to a 25kΩ pull-up resistor and will default
to logic HIGH state if open.
2, 5
3
VT0
4
VREF-AC0
7
SE-TERM
8, 10
CLK1, /CLK1
9
VBB1
12
13, 23, 28,
33, 43
44
42, 41
40, 39
38, 37
36, 35
32, 31
30, 29
27, 26
25, 24
21, 20
19, 18
17, 16
15, 14
EN
VCC
CLK_SEL
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
Q9, /Q9
Q10, /Q10
Q11, /Q11
Differential LVDS Outputs: These LVDS output pairs are the precision, low skew
copies of the selected input. Please refer to the, “Truth Table” below for details.
Unused output pairs should be terminated with 100Ω across the pair. Each output is
designed to drive 325mV into 100Ω. See the “LVDS Output Interface Applications”
section for more details.
March 2005
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hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89113U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .......................... –0.5V to +4.0V
Input Voltage
(Differential Input CLK0, CLK1
(4, 5)
).. –0.5V to V
CC
Current on Reference Voltage Outputs
Source or sink current on VREF-AC0, VBB1.....±2mA
Termination Current
Source or sink current on VT0 ................±100mA
Input Current
Source or sink current on CLK0, /CLK0 ...±50mA
Lead Temperature (soldering, 20 sec.) .......... +260°C
Storage Temperature (T
s
) ................. –65°C to 150°C
Operating Ratings
(2)
Supply Voltage (V
CC
).................. +2.375V to +2.625V
Ambient Temperature (T
A
)................ –40°C to +85°C
Package Thermal Resistance
(3)
MLF™ (θ
JA
)
Still-Air ................................................ 24°C/W
MLF™ (ψ
JB
)
Junction-to-Board ................................. 8°C/W
DC Electrical Characteristics
(6)
T
A
= –40°C to +85°C, unless otherwise stated.
Symbol
V
CC
I
CC
R
IN
R
DIFF_IN
V
IH
Parameter
Power Supply
Power Supply Current
Input Resistance
(CLK0-to-V
T
)
Differential Input Resistance
(CLK0-to-/CLK0)
Input High Voltage
(CLK0, /CLK0)
(CLK1, /CLK1)
V
IL
Input Low Voltage
(CLK0, /CLK0)
(CLK1, /CLK1)
V
IN
Input Voltage Swing
(CLK0, /CLK0)
(CLK1, /CLK1)
V
DIFF_IN
Differential Input Voltage Swing
|CLK0-to-/CLK0|
|CLK1-to-/CLK1|
V
T0
V
REF-AC0
V
BB1
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
θ
JA
and
Ψ
JB
values are determined for a 4-layer board in still-air, unless otherwise stated.
4. SE-TERM not connected.
5. Using single-ended TTL/CMOS input signals, SE-TERM connects to GND. See Figure 4f.
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Condition
No load, max. V
CC
Min
2.375
Typ
240
Max
2.625
330
55
110
Units
V
mA
Ω
Ω
45
90
50
100
1.2
Note 4
Note 5
0.2
1.2
0.1
Note 4
Note 5
See Figure 1a.
See Figure 1a.
See Figure 1b.
See Figure 1b.
0.2
0
0.1
0.2
0.2
0.4
V
CC
V
CC
3.6
V
CC
V
V
V
V
V
V
CC
V
V
V
V
CLK0-to-V
T0
(CLK0, /CLK0)
Output Reference Voltage
Output Reference Voltage
V
CC
–1.3
V
CC
–1.525
V
CC
–1.2
V
CC
–1.425
1.28
V
CC
–1.1
V
CC
–1.325
V
V
V
March 2005
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or (408) 955-1690
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