Supertex inc.
Low Harmonic Distortion 32-Channel SPST
High Voltage Analog Switch
Features
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32-channel high voltage analog switch
3.3V or 5.0V CMOS input logic level
30MHz data shift clock frequency
HVCMOS technology for high performance
Very low quiescent power dissipation (10µA)
Low parasitic capacitance
DC to 50MHz analog signal frequency
-60dB typical off isolation at 5.0MHz
CMOS logic circuitry for low power
Excellent noise immunity
Cascadable serial data register with latches
Flexible operating supply voltages
Medical ultrasound imaging
NDT metal flaw detection
Piezoelectric transducer drivers
Inkjet printer heads
Optical MEMS modules
HV2802
General Description
The HV2802 is a low charge injection, 32-channel, high voltage
analog switch intended for use in applications requiring high
voltage switching controlled by low voltage control signals,
such as medical ultrasound imaging, driving piezoelectric
transducers, and printers.
Input data are shifted into a 32-bit shift register that can then
be retained in a 32-bit latch. To reduce any possible clock
feed through noise, the latch enable bar should be left high
until all bits are clocked in. Data are clocked in during the
rising edge of the clock. Using HVCMOS technology, this
device combines high voltage bilateral DMOS switches and
low power CMOS logic to provide efficient control of high
voltage analog signals.
The device is suitable for various combinations of high
voltage supplies, e.g., V
PP
/V
NN
: +40V/-160V, +100V/-100V,
and +160V/-40V.
Applications
Block Diagram
Latches
D
LE
CLR
CLK
Level
Output
Shifters Switches
SW0A
SW0B
SW1A
SW1B
SW2A
SW2B
D
LE
CLR
DIN
32-Bit
Shift
Register
D
LE
CLR
DOUT
D
LE
CLR
D
LE
CLR
VDD
GND
LE CLR
VNN VPP
SW30A
SW30B
SW31A
SW31B
Doc.# DSFP-HV2802
NR120413
Supertex inc.
www.supertex.com
HV2802
Ordering Information
Part Number
HV2802LB-G
Package Option
78-Ball LFGA
Packing
260/Tray
-G denotes a lead (Pb)-free / RoHS compliant package
Pin Configuration
1
2
3
4 5
6
7
8 9 1 0 11 1 2 1 3
A
B
C
D
E
Absolute Maximum Ratings
Parameter
V
DD
logic supply
V
PP
-V
NN
differential supply
V
PP
positive supply
V
NN
negative supply
Logic input voltage
Analog signal range
Peak analog signal current/channel
Storage temperature
Power dissipation
Value
-0.5V to +6.5V
220V
-0.5V to V
NN
+200V
+0.5V to -200V
-0.5V to V
DD
+0.3V
V
NN
to V
PP
3.0A
-65°C to 150°C
1.5W
78-Ball LFGA
Top View
F
G
H
J
K
L
M
N
(Balls on the bottom of the package.)
Product Marking
HV2802LB
LLLLLLLLL
YYWW
AAA CCC
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Typical Thermal Resistance
Package
78-Ball LFGA
θ
ja
36
O
C/W
Package may or may not include the following marks: Si or
78-Ball LFGA
Recommended Operating Conditions
Sym
V
DD
V
PP
V
NN
V
IH
V
IL
V
SIG
T
A
Parameter
Logic power supply voltage
Positive high voltage supply
Negative high voltage supply
High level input voltage
Low level input voltage
Analog signal voltage peak-to-peak
Operating free air temperature
Value
3.0V to 5.5V
+40V to V
NN
+200V
-40V to -160V
0.9V
DD
to V
DD
0V to 0.1V
DD
V
NN
+10V to V
PP
-10V
0
O
C to 70
O
C
Notes:
1.
Power up/down sequence is arbitrary except GND must be powered-up first and
powered-down last.
2.
V
SIG
must be V
NN
≤ V
SIG
≤ V
PP
or floating during power up/down transition.
3.
Rise and fall times of power supplies V
DD
, V
PP
, and V
NN
should not be less than 1.0msec.
Doc.# DSFP-HV2802
NR120413
2
Supertex inc.
www.supertex.com
HV2802
DC Electrical Characteristics
(Over recommended operating conditions unless otherwise specified )
Sym
Parameter
0
O
C
Min
-
-
R
ONS
Small signal switch
ON-resistance
-
-
-
-
ΔR
ONS
R
ONL
I
SOL
V
OS
I
NNQ
I
NNQ
f
SW
I
SW
I
PPQ
I
PPQ
Small signal switch
ON-resistance matching
Large signal switch
ON-resistance
Switch off leakage per switch
DC offset switch off
DC offset switch on
Quiescent V
PP
supply current
Quiescent V
PP
supply current
Switch output peak current
Quiescent V
NN
supply current
Quiescent V
NN
supply current
Output switching frequency
-
-
-
-
-
-
-
-
-
-
-
-
I
PP
Average V
PP
supply current
-
-
-
I
NN
Average V
NN
supply current
-
-
I
DDQ
I
SINK
C
IN
I
SOR
I
DD
Average V
DD
supply current
Data out source current
Data out sink current
Logic input capacitance
-
-
0.45
0.45
-
Quiescent V
DD
supply current
Max
30
25
25
18
23
22
20
-
5.0
300
500
-
-
-
-
3.0
-
16
14
14
16
14
14
8.0
10
-
-
10
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+25
O
C
Typ
26
22
22
18
20
16
5.0
15
1.0
100
100
10
-10
10
-10
3.0
-
-
-
-
-
-
-
-
-
Max
38
27
27
24
25
25
20
-
10
300
500
50
-50
50
-50
2.0
50
20
14
14
20
14
14
8.0
10
-
-
10
+70
O
C
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.40
0.40
-
Max
48
32
30
27
30
27
20
-
15
300
500
-
-
-
-
2.0
-
22
14
14
22
14
14
8.0
10
-
-
10
mA
μA
mA
mA
pF
mA
mA
%
Ω
μA
mV
μA
μA
A
Ω
Unit Conditions
V
PP
= +40V,
I
SIG
= 200mA V
NN
= -160V
V
PP
= +100V,
I
SIG
= 200mA V
NN
= -100V
V
PP
= +160V,
I
SIG
= 200mA V
NN
= -40V
I
SIG
= 5.0mA
I
SIG
= 5.0mA
I
SIG
= 5.0mA
I
SIG
= 5.0mA,
V
PP
= +100V, V
NN
= -100V
V
SIG
= V
PP
-10V, I
SIG
= 1A
V
SIG
= V
PP
-10V, V
NN
+10V
No load
All switches off
All switches on,
I
SW
= 5.0mA
V
SIG
duty cycle < 0.1%
kHz Duty cycle = 50%
V
PP
= +40V, All output
V
NN
= -160V switches are
V
PP
= +100V, turning on
V
NN
= -100V and off at
V
PP
= +160V, 50kHz with
no load
V = -40V
V
PP
= +40V, All output
V
NN
= -160V switches are
V
PP
= +100V, turning on
V
NN
= -100V and off at
V
PP
= +160V, 50kHz with
no load
V = -40V
All logic inputs are static
V
OUT
= V
DD
-0.7V
---
V
OUT
= 0.7V
f
CLK
= 5.0MHz, V
DD
= 5.0V
NN
NN
0.45 0.70
0.45 0.70
-
-
Doc.# DSFP-HV2802
NR120413
3
Supertex inc.
www.supertex.com
HV2802
AC Electrical Characteristics
(Over recommended operating conditions unless otherwise specified)
Sym
t
SD
t
WLE
t
DO
t
WCLR
t
SU
t
H
f
CLK
t
R
, t
F
t
OFF
dv/dt
t
ON
Parameter
Set up time before LE rises
Time width of LE
Clock delay time to data out
Time width of CLR
Set up time data to clock
Hold time data from clock
Clock frequency
Clock rise and fall times
Turn on time
Turn off time
Maximum V
SIG
slew rate
0
O
C
Min
25
56
12
8.0
8.0
55
21
7.0
5.0
7.0
-
-
-
-
-
-
-
-
-30
-58
Switch crosstalk
Output switch isolation diode
current
-60
-
-
-
-
-
Output voltage spike SWA
-
-
-
-
-
-
Output voltage spike SWB
-
-
-
-
-
Charge injection
-
-
Max
-
-
-
40
30
-
-
-
-
-
8
20
50
5.0
5.0
20
20
20
-
-
-
300
14
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min
25
-
-
8.0
8.0
55
21
7.0
5.0
7.0
-
-
-
-
-
-
-
-
-30
-58
-60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+25
O
C
Typ
-
56
12
19
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-33
-60
-70
-
9.0
12
-
-
-
-
-
-
-
-
-
-
-
-
820
600
350
Max
-
-
-
40
30
-
-
-
-
-
8
20
50
5.0
5.0
20
20
20
-
-
-
300
14
17
+150
-150
+150
-150
+150
-150
+150
-150
+150
-150
+150
-150
-
-
-
+70
O
C
Min
25
56
12
8.0
8.0
55
21
7.0
5.0
7.0
-
-
-
-
-
-
-
-
-30
-58
-60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
40
30
-
-
-
-
-
8
20
50
5.0
5.0
20
20
20
-
-
-
300
14
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pC
mV
mV
dB
mA
pF
Unit Conditions
ns
ns
ns
ns
ns
ns
MHz
ns
μs
---
V
DD
= 3.0V
V
DD
= 3.0V
V
DD
= 5.0V
---
V
DD
= 3.0V
V
DD
= 3.0V
V
DD
= 3.0V
V
DD
= 5.0V
V
DD
= 5.0V
V
DD
= 5.0V
---
V
DD
= 5.0V
V
SIG
= V
PP
-10V,
R
LOAD
= 10kΩ
V
PP
= +40V, V
NN
= -160V
V/ns V
PP
= +100V, V
NN
= -100V
f = 5.0MHz,
1.0kΩ//15pF load
V
PP
= +160V, V
NN
= -40V
K
O
K
CR
I
ID
Off isolation
dB
f = 5.0MHz, 50Ω load
f = 5.0MHz, 50Ω load
300ns pulse width,
2.0% duty cycle
V
SIG
= 0V, f = 1.0MHz
V
PP
= +40V, V
NN
= -160V
R
LOAD
= 50Ω
V
PP
= +100V, V
NN
= -100V
R
LOAD
= 50Ω
V
PP
= +160V, V
NN
= -40V
R
LOAD
= 50Ω
V
PP
= +40V, V
NN
= -160V
R
LOAD
= 50Ω
V
PP
= +100V, V
NN
= -100V
R
LOAD
= 50Ω
V
PP
= +160V, V
NN
= -40V
R
LOAD
= 50Ω
V
PP
= +40V, V
NN
= -160V
V
PP
= +100V, V
NN
= -100V
V
PP
= +160V, V
NN
= -40V
C
SG(OFF)
Off capacitance SW to GND
+V
SPK
-V
SPK
-V
SPK
-V
SPK
-V
SPK
-V
SPK
-V
SPK
QC
C
SG(ON)
On capacitance SW to GND
+V
SPK
+V
SPK
+V
SPK
+V
SPK
+V
SPK
Doc.# DSFP-HV2802
NR120413
4
Supertex inc.
www.supertex.com
Embedded System
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