PI4ULS5V4557
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Dual SIM/Smart Card Power Supply and Interface Signal Switch
Features
Description
The PI4ULS5V4557 provides the power conversion and
signal level translation needed for advanced (2.5G and
3G) cellular telephones to interface with 1.8V and 3V
subscriber identity modules (SIMs). The device meets
all requirements for 1.8V or 3V SIMs and contains LDO
regulators to power 1.8V or 3V SIM cards from a 2.7V
to 5.5V input. The output voltages can be set using the
voltage selection pins and up to 50mA of load current
can be supplied. A channel select pin determines which
channel is open for communication.
Internal level translators allow controller operating
with supplier as low as
1.4V to
interface with 1.8V or
3V Smart Cards. Battery life is maximized by a low
operating current of 40μA and a shutdown current of
less than 1μA.
Power Management and Control for two SIM Cards
or Smart Cards
Independent 1.8V/3V VCC Control for Both Cards
Supports Simultaneous Powering of Both Cards
Fast channel Switching
Automatic Level Translation
Fast rise time by current pull up
Built-In Fault Protection Circuitry
Automatic Activation/Deactivation Sequencing
Low Operating/Shutdown Current
>8kV ESD on SIM Card Pins
Meets EMV Fault Tolerance Requirements
Packaging (Pb-free & Green): 16-Lead TQFN3x3
Pin Assignment
CLK2
RST2
I/O2
EN
16
V
CC2
V
DD
C
15
14
13
12
11
10
9
M0
M1
CLKIN
RSTIN
Applications
1
2
3
4
5
CLK1
6
RST1
7
I/O1
8
DATA
GSM, TD-SCDMA and other 3G+ Cellular Phones
Wireless Point-to-Sale Terminals
Multiple SIM Card Interfaces
17
V
BAT
V
CC1
Note:
16-Lead (3mmx3mm) Plastic QFN Exposed Pad (pin 17)
is GND, Must Be Soldered to PCB.
12-12-0004
1
PT0395-1
01/05/13
PRELIMINARY INFORMATION: COMPANY CONFIDENTIAL
PI4ULS5V4557
Dual SIM/Smart Card Power Supply and
Interface Signal Switch
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Pin Description
Pin
2
3
4, 1
5, 16
6, 15
7, 14
8
9
10
13
11,12
17
Name
V
DD
V
BAT
V
CC1
, V
CC2
CLK1,
CLK2
RST1, RST2
I/O1,
I/O2
DATA
RSTIN
CLKIN
EN
M1, M0
GND
Type
P
I
O
O
O
I/O
I/O
I
I
I
I
P
Description
Power Input. Control logic power supply voltage input of devices.
Power Input. Analog section power supply voltage input of devices.
Power Outputs. 1.8V or 3V voltage output for respective SIM /Smart cards’ power
supply V
CC
pin.
Clock Outputs. Connect CLK1/2 pins to respective SIM/Smart cards’ CLK pin.
CLK1/2 signals are derived from the CLKIN pin.
Reset Outputs. Connect RST1/2 pins to respective SIM/Smart cards’ RST pin.
RST1/2 signals are derived from the RSTIN pin.
Data Ports. Connect I/O1, I/O2 pins to respective SIM/Smart cards’ I/O pin.
Communication path can be set from DATA to I/O1 or from DATA to I/O2.
Data Port. I/O1 or I/O2 pin transmits/receives data to/from the DATA pin.
Reset Input. Reset signal is transmitted from RSTIN to RST1 or RST2.
Clock Input. Clock signal is transmitted from CLKIN to CLK1 or CLK2.
V
CC1
, V
CC2
Enable Control Inputs.
Voltage Selection Inputs. V
CC1
, V
CC2
both have two voltage values 1.8V and 3V,
and V
CC1
, V
CC2
voltage values can be selected at same time. Details see below Truth
Table.
Ground. Exposed pad of the package bottom.
Truth Table
M1
0
0
1
1
M0
0
1
0
1
Selected Channel/Voltage
Channel 1/1.8V (V
CC1
=1.8V)
Channel 1/3V (V
CC1
=3V)
Channel 2/1.8V (V
CC2
=1.8V)
Channel 2/3V (V
CC2
=3V)
Maximum Ratings
Storage Temperature ............................................................... -65℃ to +150℃
Ambient Temperature ............................................................... -40℃ to +85℃
ESD(HBM) for I/O pins ............................................................................. 8KV
ESD(HBM) for all pins ........................................................................... 7.5KV
V
BAT
, V
DD
, DATA, RSTIN, CLKIN,
EN, M0, M1
to GND
........
-0.5V to +6V
I/O1, CLK1, RST1
............................................................-0.5V
to V
CC1
+0.5V
I/O2, CLK2, RST2
............................................................-0.5V
to V
CC2
+0.5V
I
CC1, 2
.........................................................................................................80mA
V
CC1
,
2
Short Circuit Duration……………………………………….Indefinite
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. The device is guaranteed to meet performance
specifications from 0° to 85° Specification over
C
C.
the -40° to 85° operating temperature range are
C
C
assured by design, characterization and correlation
with statistical controls.
3. I
CC1, 2
based on long-term current density
limitation.
12-12-0004
2
PT0395-1
01/05/13
PRELIMINARY INFORMATION: COMPANY CONFIDENTIAL
PI4ULS5V4557
Dual SIM/Smart Card Power Supply and
Interface Signal Switch
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DC Electrical Characteristics
(V
BAT
=3.3V, V
DD
=1.8V, C
1
=C
2
=1
μ
F,
T
A
= –40° to 85° unless otherwise noted.)
C
C,
Parameter
Description
Test Conditions
Input Power Supply
V
BAT
V
BAT
Operating Voltage
-
V
CC1
=3V, V
CC2
=0V, I
CC1
=0A
I
BAT
V
BAT
Operating Current
V
CC1
=1.8V, V
CC2
=0V, I
CC1
=0A
V
DD
V
DD
Operating Voltage
-
I
DD
V
DD
Operating Current
-
I
DDS
V
DD
Shutdown Current
-
I
BATS
V
BAT
Shutdown Current
V
DD
=0V
SIM Card Supplies
3V Mode. 0mA<I
CC1, 2
<50mA
Output Voltage
V
CC1, 2
1.8V Mode. 0mA<I
CC1, 2
<30mA
Channel Turn on Time
I
CC1, 2
=0mA, EN to I
O1/2
CLK1, 2
V
OL
Low Level Output Voltage
Sink current =-200μA
V
OH
High Level Output Voltage
Rise/Fall Time
CLK1, 2 Frequency
RST1, 2
V
OL
V
OH
I/O1, 2
V
OL
V
OH
Low Level Output Voltage
High Level Output Voltage
Rise/Fall Time
Low Level Output Voltage
High Level Output Voltage
Rise/Fall Time
Short-Circuit current
DATA
V
OL
V
OH
Low Level Output Voltage
High Level Output Voltage
Source current =200μA
Loaded with 50pF (10% to 90%)
Min
2.7
-
1.4
-
-
-
2.85
1.71
-
-
V
CC1, 2
-
0.2
-
10
-
V
CC1, 2
-
0.2
-
-
0.85×
V
CC1, 2
Typ.
-
40
-
4
0.1
0.1
3.00
1.8
1
-
-
-
-
-
-
-
-
-
300
3.5
-
-
125
-
-
-
Max
5.5
100
3.6
15
1
1
3.15
1.89
2.5
0.2
-
16
Unit
V
μA
V
μA
V
ms
Ｖ
Ｖ
ns
MHz
Ｖ
Ｖ
Sink current =-200μA
Source current =200μA
Loaded with 50pF (10% to 90%)
Sink current =-1mA (V
DATA
=0V)
Source current =20μA
(V
DATA
=V
DD
)
Loaded with 50pF (10% to 90%)
V
DATA
=0V
Sink current =-500μA (V
I/O1, 2
=0V)
Source current =20μA
(V
I/O1, 2
=V
CC1, 2
)
Loaded with 50pF (10% to 90%)
-
-
-
0.2
100
0.3
-
500
10
0.3
-
500
0.15×
V
DD
-
1
ns
Ｖ
Ｖ
ns
mA
Ｖ
Ｖ
ns
Ｖ
Ｖ
μA
-
-
-
0.8×
V
DD
-
-
0.85×
V
DD
Rise/Fall Time
EN, RSFN, CLKIN, MO, M1
V
IL
V
IH
I
IL
(I
IH
)
Low Input Threshold
High Input Threshold
Input Current
-1
12-12-0004
3
PT0395-1
01/05/13
PRELIMINARY INFORMATION: COMPANY CONFIDENTIAL
PI4ULS5V4557
Dual SIM/Smart Card Power Supply and
Interface Signal Switch
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Function Block Diagram
V
DD
2
V
CC1
4
LDO1
V
DD
V
BAT
3
LDO2
1
V
CC2
I/O1
7
14
I/O2
RST1
6
15
RST2
CLK1
5
16
CLK2
DATA
RSTIN
CLKIN
8
9
10
V
DD
Control Logic
17
GND
13
EN
12
M0
11
M1
Function Description
V
DD
(Pin 2):
Power. The Control logic is referring to the voltage.
V
BAT
(Pin 3):
Power. The supply voltage input of analog sections.
V
CC1
, V
CC2
(Pins 4, 1):
Two power supply outputs to the respective card sockets V
CC
pins and both can be set to 0V, 1.8V or 3V
via the M0, M1and EN inputs. Only one of V
CC1
, V
CC2
will be active at a time.
CLK1, CLK2 (Pins 5, 16):
Two clock outputs to the respective card sockets CLK pins and the clock signals are derived from the
CLKIN pin with level shift functions. The CLK1, CLK2 pins are gated off until V
CC1
, V
CC2
attain their correct values.
RST1, RST2 (Pins 6, 15):
Two reset outputs to the respective card sockets RST pins and the reset signals are derived from the
RSTIN pin with level shift functions. The RST1, RST2 pins are gated off until V
CC1
, V
CC2
attain their correct values. When a card
is deselected, the sate of its RST is latched up to its current state.
I/O1, I/O2 (Pins 7, 14):
Two data outputs/inputs to the respective card sockets I/O pins, transmit /receive data to/from the DATA
12-12-0004
4
PT0395-1
01/05/13
PRELIMINARY INFORMATION: COMPANY CONFIDENTIAL
PI4ULS5V4557
Dual SIM/Smart Card Power Supply and
Interface Signal Switch
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
pin with level shift functions. The I/O1, I/O2 pins are gated off until V
CC1
, V
CC2
attain their correct values.
DATA (Pin 8):
Input/Output. Connect this pin to microcontroller side I/O pin. The DATA pin provides the bidirectional
communication path to both cards. Only one of cards may be selected to communicate via the DATA pin at a time. The pin
possesses a weak pull-up current source, allowing the controller to use an open drain output and maintain a HIGH state during
shutdown, as long as V
DD
is powered.
RSTIN (Pin 9):
Input. Supply the reset signal to the cards through RST1, RST2. It is level shifted and transmitted directly to the
RST pin of the selected card.
CLKIN (Pin 10):
Input. Supply the clock signal to the cards through CLK1, CLK2. It is level shifted and transmitted directly to
the CLK pin of the selected card.
M0, M1 (Pins 12, 11):
Inputs. The M0, M1 pins select which set of SIM/smart card pins are active and the voltage level (1.8V or
3V) of VCC1, VCC2. Detail please sees below
Channel and Voltage Truth Table.
EN (Pins 13):
Inputs. The EN pin shuts down the chip when LOW.
EXPOSED PAD (17):
Chip Ground. This ground pad must be soldered directly to a PCB ground plane.
The PI4ULS5V4557 features two independent SIM/Smart Card channels. Only one of these channels may be open for
communication at a time. Each channel is able to product two voltage levels, 1.8V and 3V. The channel selection and voltage
selection are controlled by the EN, M0 and M1 pins as shown in the table below:
Channel and Voltage Truth Table
EN
1
1
1
1
0
Bidirectional Channels
The bidirectional channels are level shifted to the appropriate V
CC1, 2
voltages at the I/O1, 2 pins. An NMOS pass transistor
performs the level shifting. The gate of the NMOS transistor is biased such that the transistor is completely off when both sides
have relinquished the channel. If one side of the channel asserts a LOW, then the transistor will convey LOW to the other side.
When a channel is selected, it becomes a candidate to drive data on the DATA pin and likewise receive data from the DATA pin.
When a channel is deselected, it’s I/O1 (or I/O2) pin will be pulled LOW and communication with the DATA pin will be disabled.
If both channels are disabled, a weak pull-up ensures that the DATA pin is held HIGH, as long as V
DD
is powered.
Auto Pull-Up Current Sources
Internal auto pull-up current source will confirm the signal pass through bidirectional pins (DATA, I/O1, 2) and fast the signal rise
time when normal data transmit/receive from DATA to I/O1 (I/O2) .
Reset Channels
When a channel is selected, the reset channel provides a level shifted path from the RSTIN pin to the RST pin of the selected card.
PI4ULS5V4557’s reset pin is pulled LOW when a channel is deselected.
Activation/Deactivation
Activation and deactivation sequencing is handled by built-in circuitry. Each channel may be activated or deactivated
independently of the other. The activation sequence for each channel is initiated by bringing the EN pin HIGH. The activation
sequence is outlined below:
1. The RST, CLK and I/O pins are held LOW.
2. VCC is enabled.
3. After VCC is stable at its selected level, the I/O and RST channels are enabled.
4. The clock channel is enabled on the rising edge of the second clock cycle after the I/O pin is enabled.
The deactivation sequence is initiated by bringing the EN pin LOW. The deactivation sequence is outlined below:
1. The reset channel is disabled and RST is brought LOW.
2. The clock channel is disabled and the CLK pin is brought LOW two clock cycles after EN is brought LOW. If the clock is not
running, the clock channel will be disabled approximately 9μs after the EN pin is brought LOW.
12-12-0004
5
PT0395-1
01/05/13
M1
0
0
1
1
×
M0
0
1
0
1
×
Selected Channel/Voltage
Channel 1/1.8V (V
CC1
=1.8V)
Channel 1/3V (V
CC1
=3V)
Channel 2/1.8V (V
CC2
=1.8V)
Channel 2/3V (V
CC2
=3V)
Channel 1 and 2 Disabled
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