8-Output Very Low Phase Jitter
HCSL Fanout Buffer
8INT31H800A
DATA SHEET
General Description
The 8INT31H800A is an 8-output very high performance HCSL
fanout buffer for High Performance Interconnect applications. It can
also be used at speeds up to 350MHz. There are four OE pins on the
device, each controlling two outputs.
Features/Benefits
• Extremely low additive phase jitter; supports DB800H
requirements
• 3.3V operation; standard industry power supply
• Four OE pins each controlling two outputs; easy control of clocks
to CPU sockets
• Universal differential input; can be driven by HCSL or LVPECL
clock sources
• 1MHz to 350MHz operating frequency; covers all popular Ethernet
frequencies
• Space saving 32-pin 5x5mm VFQFN; minimal board space
Recommended Application
DB800H
Output Features
• Eight HCSL differential pairs
Key Specifications
• Qx output-to-output skew within a pair: 22ps (typical)
• Qx output-to-output skew across all outputs: 32ps (typical)
• RMS additive phase jitter: 65fs (typical)
Block Diagram
vOE_01#
Q(0:1)
vOE_23#
Q(2:3)
nCLK_IN
CLK_IN
Q(4:5)
vOE_45#
Pin Assignment
vOE_45#
vOE_23#
vOE_01#
V
DDO3.3
V
DDO3.3
25
24
23
22
GNDO
32
31
30
29
28
27
26
Q0
nQ0
Q1
nQ1
Q2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GNDO
IREF
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
8INT31H800A
21
20
19
18
17
Q(6:7)
vOE_67#
nQ2
Q3
nQ3
vOE_67#
nCLK_IN
V
DDO3.3
GNDO
GND
32-pin, 5mm x 5mm VFQFN Package
v prefix indicates internal 50kΩ
pull-down
resistor
8INT31H800A REVISION 2 12/09/14
1
CLK_IN
©2014 Integrated Device Technology, Inc.
V
DDO3.3
V
DD3.3
8INT31H800A DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Name
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
V
DDO3.3
vOE_67#
CLK_IN
nCLK_IN
GND
V
DD3.3
GNDO
V
DDO3.3
nQ7
Q7
nQ6
Q6
nQ5
Q5
nQ4
Q4
V
DDO3.3
GNDO
IREF
Output
Output
Output
Output
Output
Output
Output
Output
Power
Input
Input
Input
GND
Power
GND
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
GND
Output
Pulldown
Type
Pin Description
Non-inverting output of Differential Pair 0.
Inverting output of Differential Pair 0.
Non-inverting output of Differential Pair 1.
Inverting output of Differential Pair 1.
Non-inverting output of Differential Pair 2.
Inverting output of Differential Pair 2.
Non-inverting output of Differential Pair 3.
Inverting output of Differential Pair 3.
Power supply for outputs, nominal 3.3V.
Active Low input for enabling outputs 6 and 7.
0 = enable outputs, 1 = disable outputs
True Input for differential reference clock.
Complementary Input for differential reference clock.
Ground pin.
Power supply, nominal 3.3V.
Ground pin for outputs.
Power supply for outputs, nominal 3.3V.
Inverting output of Differential Pair 7.
Non-inverting output of Differential Pair 7.
Inverting output of Differential Pair 6.
Non-inverting output of Differential Pair 6.
Inverting output of Differential Pair 5.
Non-inverting output of Differential Pair 5.
Inverting output of Differential Pair 4.
Non-inverting output of Differential Pair 4.
Power supply for outputs, nominal 3.3V.
Ground pin for outputs.
This pin establishes the reference for the differential current-mode output pairs. It requires
a fixed precision resistor to ground. 475 is the standard value for 100 differential
impedance. Other impedances require different values. See data sheet.
Pulldown
Active Low input for enabling outputs 0 and 1.
0 = enable outputs, 1 = disable outputs
Active Low input for enabling outputs 2 and 3
0 = enable outputs, 1 = disable outputs
Active Low input for enabling outputs 4 and 5.
0 = enable outputs, 1 = disable outputs
Ground pin for outputs.
Power supply for outputs, nominal 3.3V.
28
vOE_01#
Input
29
vOE_23#
Input
Pulldown
30
31
32
vOE_45#
GNDO
V
DDO3.3
Input
GND
Power
Pulldown
8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER
2
REVISION 2 12/09/14
8INT31H800A DATA SHEET
Table 2A. Output Enable (OE) Functionality Table
1
CLK_IN
Running
Running
Not Running
vOE_x# Pin
1
0
X
Qx
Low
2
Running
X
nQx
Low
2
Running
X
Table 2B. Power Connections
1
Pin Number
V
DDx
14
9, 16, 25, 32
GND
13
15, 26, 31
Core Power Supply
Output Power Supply
Description
NOTE 1: vOE_X# denotes: vOE_01#, vOE_23#, vOE_45#,
vOE67#.
NOTE 2: The outputs are tristated and the termination networks
pulls them low.
NOTE 1: V
DDx
denotes either V
DD3.3
or V
DDO3.3
.
REVISION 2 12/09/14
3
8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER
8INT31H800A DATA SHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 8INT31H800A. These ratings, which are standard values for IDT
commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect
product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Symbol
V
DDx
V
IL
V
IH
Outputs (V
O
)
T
S
T
J
ESD (HBM)
ESD (CDM)
Storage Temperature
Junction Temperature
ESD protection
2
Human Body Model
Charged Device Model
2000
1000
-65
Parameter
3.3V Supply Voltage
1
Input Low Voltage
Input High Voltage
GND - 0.5
3.6
3.6
150
125
Test Conditions
Minimum
Typical
Maximum
3.6
Units
V
V
V
V
°C
°C
V
V
NOTE 1: V
DDx
denotes either V
DD3.3
or V
DDO3.3.
NOTE 2: According to JEDEC/JS-001-2012/JESD22-C101E.
Electrical Characteristics
Table 3A. Input/Supply/Common Parameters,
Supply Voltage V
DDx
1
= 3.3 V ±5%, T
A
= T
IND
2
Symbol
T
IND
V
IH
V
IL
Parameter
Ambient Operating Temperature
Input High Voltage
Input Low Voltage
Test Conditions
Industrial Range
vOE_01#, vOE_23#
vOE_45#, vOE_67#
vOE_01#, vOE_23#
vOE_45#, vOE_67#
vOE_01#, vOE_23#
vOE_45#, vOE_67#
V
DD3.3
= V
IN
= 3.465V
vOE_01#, vOE_23#
vOE_45#, vOE_67#
V
DD3.3
= 3.465V, V
IN
= 0V
-5
1
350
7
vOE_01#, vOE_23#
vOE_45#, vOE_67#
Capacitance
CLK_IN, nCLK_IN
Output Pin Capacitance
OE# Latency
4
Input Clock must be running
4
5
3
6
12
Minimum
-40
2.2
GND - 0.3
Typical
25
Maximum
85
V
DD3.3
+ 0.3
0.8
Units
°C
V
V
I
IH
Input High Current
150
A
I
IL
F
max
L
pin
C
IN
C
INDIF_IN
C
OUT
t
LATOE
Input Low Current
Maximum Input Frequency
3
Pin Inductance
A
MHz
nH
pF
pF
pF
clocks
NOTE 1: V
DDx
denotes either V
DD3.3
or V
DDO3.3
.
NOTE 2: Guaranteed by design and characterization, not 100% tested in production.
NOTE 3: Signal edge is required to be monotonic when transitioning through this region.
NOTE 4: Time from de-assertion until outputs are stopped or time from assertion until outputs are running.
8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER
4
REVISION 2 12/09/14
8INT31H800A DATA SHEET
Table 3B. Clock Input Parameters,
Supply Voltage V
DD
x
1
= 3.3 V ±5%, T
A
= T
IND
,
Symbol
V
PP
V
CMR
dv/dt
I
IN
d
tin
Parameter
Peak-to-Peak Voltage
Common Mode
Input Voltage
2, 3
Input Slew Rate
4
Input Leakage Current
Input Duty Cycle
CLK_IN,
nCLK_IN
CLK_IN,
nCLK_IN
Measured Differentially
V
IN
= V
DD3.3 ,
V
IN
= GND
Measurement from
Differential Waveform
Test Conditions
Minimum
0.3
GND + 0.3
0.4
-5
40
Typical
Maximum
1.0
V
DD3.3
- 1
8
5
60
Units
V
V
V/ns
A
NOTE 1: V
DDx
denotes either V
DD3.3
or V
DDO3.3.
NOTE 2: Common mode voltage is defined as the crosspoint.
NOTE 3: Input voltage cannot be less than GND - 300mV or more than V
DD3.3.
NOTE 4: Slew rate measured through ±75mV window centered around differential zero.
Table 3C. Qx HCSL Differential Outputs,
Supply Voltage V
DDx
1
= 3.3 V ±5%, T
A
= T
IND
Symbol
dv/dt
ΔTrf
V
HIGH
V
Low
V
max
V
min
Δ-V
cross
Parameter
Slew Rate
2, 3
Rise/Fall Time Matching
4
Voltage High
5
Voltage Low
5
Max. Voltage
5
Min. Voltage
5
Crossing Voltage (var)
5, 7
Rise/Fall Time Matching
Statistical Measurement on Single-ended Signal
using Oscilloscope Math Function
Measurement on Single-ended Signal
using Absolute Value
650
-150
Test Conditions
Minimum
0.6
Typical
Maximum
4
20
875
150
1150
-300
240
550
140
Units
V/ns
%
mV
mV
mV
mV
mV
V
cross_abs
Crossing Voltage (abs)
6
NOTE 1: V
DDx
denotes either V
DD3.3
or V
DDO3.3
.
NOTE 2: Measured from differential waveform.
NOTE 3: Slew rate is measured through the V
swing
voltage range centered around differential 0V. This results in a
±
150mV window
around differential 0V.
NOTE 4: Rise/Fall matching derived using the following, 2*(T
RISE
- T
FALL
) / (T
RISE
+ T
FALL
)
NOTE 5: Measured from single-ended waveform.
NOTE 6: V
cross
is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
NOTE 7: The total variation of all V
cross
measurements in any system. Note that this is a subset of V
_cross_min/max
(V
_cross absolute
) allowed.
The intent is to limit V
cross
induced modulation by setting V
_cross_delta
to be smaller than V
_cross absolute
.
NOTE:
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500ppm. The device will meet specifications
after thermal equilibrium has been reached under these conditions.
NOTE:
Guaranteed by design and characterization, not 100% tested in production.
REVISION 2 12/09/14
5
8-OUTPUT VERY LOW PHASE JITTER HCSL FANOUT BUFFER
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