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5P49V5935A508LTGI

Description
Clock Generators & Support Products VersaClock 5 LP Program CLK
Categorysemiconductor    Analog mixed-signal IC   
File Size445KB,32 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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5P49V5935A508LTGI Overview

Clock Generators & Support Products VersaClock 5 LP Program CLK

5P49V5935A508LTGI Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIDT (Integrated Device Technology, Inc.)
Product CategoryClock Generators & Support Products
RoHSDetails
PackagingTray
Moisture SensitiveYes
NumOfPackaging1
Factory Pack Quantity490
Programmable Clock Generator
5P49V5935
DATASHEET
Description
The 5P49V5935 is a programmable clock generator intended
for high-performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface. This is IDT’s fifth generation of programmable clock
technology (VersaClock
®
5).
The 5P49V5935 by default uses an integrated 25MHz crystal
as input reference. It also has a redundant external clock
input. A glitchless manual switchover functions allows
selection of either one as mentioned above as input reference
during normal operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I
2
C
addresses to allow multiple devices to be used in a system.
Features
Generates up to four independent output frequencies
High-performance, low phase noise PLL, < 0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1GbE and 10GbE
Four fractional output dividers (FODs)
Independent spread spectrum capability on each output
pair
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I
2
C serial programming interface
One reference LVCMOS output clock
Four universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os: LVPECL, LVDS and HCSL
Pin Assignment
OUT0_SEL_I2CB
Input frequency ranges:
– LVDS, LVPECL, HCSL differential clock input (CLKIN,
CLKINB) – 1MHz to 350MHz
Output frequency ranges:
– LVCMOS clock outputs: 1MHz to 200MHz
– LVDS, LVPECL, HCSL differential clock outputs: 1MHz
to 350MHz
OUT1B
V
DDO
0
V
DDO
1
OUT1
V
DDD
CLKIN
CLKINB
NC
NC
V
DDA
CLKSEL
24 23 22 21 20 19
1
18
2
3
4
5
6
7
8
17
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
V
DDO
2
OUT2
OUT2B
V
DDO
3
OUT3
OUT3B
each output pair
EPAD
16
15
14
13
9 10 11 12
SEL1/SDA
SEL0/SCL
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core V
DDD
, V
DDA
4 x 4 mm 24-LGA package
-40° to +85°C industrial temperature operation
SD/OE
V
DDO
4
OUT4
4 × 4 mm 24-LGA
5P49V5935 NOVEMBER 1, 2017
OUT4B
1
©2017 Integrated Device Technology, Inc.
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