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7052L20PFG8

Description
SRAM 2KX8 FOUR PORT STATIC RAM
Categorystorage   
File Size704KB,13 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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7052L20PFG8 Overview

SRAM 2KX8 FOUR PORT STATIC RAM

7052L20PFG8 Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIDT (Integrated Device Technology, Inc.)
Product CategorySRAM
RoHSDetails
Memory Size16 kbit
Organization2 k x 8
Access Time20 ns
Interface TypeParallel
Supply Voltage - Max5.5 V
Supply Voltage - Min4.5 V
Supply Current - Max250 mA
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 70 C
Mounting StyleSMD/SMT
Package / CaseTQFP-120
PackagingReel
Height1.4 mm
Length14 mm
Memory TypeSDR
TypeAsynchronous
Width14 mm
Moisture SensitiveYes
NumOfPackaging1
Factory Pack Quantity750
HIGH-SPEED
2K x 8 FourPort
TM
STATIC RAM
Features
IDT7052S/L
High-speed access
– Commercial: 20/25/35ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35ns (max.)
Low-power operation
– IDT7052S
Active: 750mW (typ.)
Standby: 7.5mW (typ.)
– IDT7052L
Active: 750mW (typ.)
Standby: 1.5mW (typ.)
True FourPort memory cells which allow simultaneous
access of the same memory locations
Fully asynchronous operation from each of the four ports:
P1, P2, P3, P4
Versatile control for write-inhibit: separate
BUSY
input to
control write-inhibit for each of the four ports
Battery backup operation—2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 120 pin Thin Quad Flatpacks and 108 pin PGA
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Description
The IDT7052 is a high-speed 2K x 8 FourPort™ Static RAM designed
to be used in systems where multiple access into a common RAM is
required. This FourPort Static RAM offers increased system performance
in multiprocessor systems that have a need to communicate in real time and
also offers added benefit for high-speed systems in which multiple access
is required in the same cycle.
The IDT7052 is also designed to be used in systems where on-chip
hardware port arbitration is not needed. This part lends itself to those
Functional Block Diagram
R/W
P1
CE
P1
OE
P1
I/O
0P1
-I/O
7P1
BUSY
P1
PORT 1
ADDRESS
DECODE
LOGIC
PORT 2
ADDRESS
DECODE
LOGIC
PORT 4
ADDRESS
DECODE
LOGIC
PORT 3
ADDRESS
DECODE
LOGIC
COLUMN
I/O
COLUMN
I/O
R/W
P4
CE
P4
OE
P4
I/O
0P4
-I/O
7P4
BUSY
P4
A
0P1
- A
10P1
A
0P4
- A
10P4
MEMORY
ARRAY
A
0P2
- A
10P2
BUSY
P2
I/O
0P2
-I/O
7P2
OE
P2
CE
P2
R/W
P2
A
0P3
- A
10P3
BUSY
P3
COLUMN
I/O
COLUMN
I/O
I/O
0P3
-I/O
7P3
OE
P3
CE
P3
R/W
P3
2674 drw 01
JULY 2016
1
©2016 Integrated Device Technology, Inc.
DSC 2674/15
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