PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
Rev. 02 — 6 July 2009
Product data sheet
1. Product profile
1.1 General description
SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in
a plastic package using TrenchMOS technology. This product is designed and qualified for
use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
High frequency computer motherboard
DC-to-DC convertors
OR-ing applicationss
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
mb
= 25 °C; V
GS
= 10 V;
see
Figure 1;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max
100
75
230
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
175 °C
drain current
total power
dissipation
gate-drain charge
Symbol Parameter
Dynamic characteristics
Q
GD
V
GS
= 10 V; I
D
= 75 A;
V
DS
= 80 V; T
j
= 25 °C;
see
Figure 11
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 9;
see
Figure 10
-
44
-
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
7.5
8.8
mΩ
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol
G
D
S
D
Description
gate
drain
source
mounting base; connected to
drain
2
1
3
Simplified outline
[1]
mb
Graphic symbol
D
G
mbb076
S
SOT404
(D2PAK)
[1]
It is not possible to make connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Package
Name
PSMN009-100B
D2PAK
Description
plastic single-ended surface-mounted package (D2PAK); 3 leads (one
lead cropped)
Version
SOT404
Type number
PSMN009-100B_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 6 July 2009
2 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
V
GSM
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
peak gate-source
voltage
source current
peak source current
pulsed; t
p
≤
50 µs; T
j
≤
150 °C;
δ
= 25 %
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1;
see
Figure 3
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≤
175 °C; T
j
≥
25 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-30
Max
100
100
20
65
75
400
230
175
175
30
Unit
V
V
V
A
A
A
W
°C
°C
V
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
I
S
I
SM
E
DS(AL)S
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
-
-
-
75
400
120
A
A
mJ
Avalanche ruggedness
non-repetitive
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 35 A; V
sup
= 15 V;
drain-source avalanche unclamped; t
p
= 0.1 ms; R
GS
= 50
Ω
energy
non-repetitive
V
GS
= 10 V; V
sup
= 15 V; R
GS
= 50
Ω;
T
j(init)
= 25 °C;
drain-source avalanche unclamped
current
I
DS(AL)S
-
75
A
120
I
der
(%)
100
03ah99
120
P
der
(%)
80
03aa16
80
60
40
40
20
0
0
30
60
90
120
150
180
T
mb
(°C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
© NXP B.V. 2009. All rights reserved.
PSMN009-100B_2
Product data sheet
Rev. 02 — 6 July 2009
3 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
10
3
I
D
(A)
10
2
03ai01
Limit R
DSon
= V
DS
/I
D
t
p
= 10 µs
100 µs
DC
10
1 ms
10 ms
100 ms
1
1
10
10
2
V
DS
(V)
10
3
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN009-100B_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 6 July 2009
4 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction
to mounting base
thermal resistance from junction
to ambient
Conditions
see
Figure 4
minimum footprint; mounted on
a printed-circuit board
Min
-
-
Typ
-
50
Max
0.65
-
Unit
K/W
K/W
1
Z
th(j-mb)
(K/W)
10
−1
δ
= 0.5
0.2
0.1
0.05
0.02
10
−2
single pulse
t
p
P
03af48
δ
=
t
p
T
t
T
10
−3
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
10
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN009-100B_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 6 July 2009
5 of 13
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