Features
•
16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (Stand-Alone, S/A off)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –142 dBm
– Tracking Sensitivity: –158 dBm
Utilizes the ARM7TDMI
®
ARM
®
Thumb
®
Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Embedded ICE (In-circuit Emulator)
128 Kbyte Internal RAM
384 Kbyte Internal ROM with u-blox GPS Firmware
6-channel Peripheral Data Controller (PDC)
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 2 External Interrupts
24 User-programmable I/O Lines
1 USB Device Port
– Universal Serial Bus (USB) V2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
– Suspend/Resume Logic
– Ping-pong Mode for Isochronous and Bulk Endpoints
2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Master/Slave SPI Interface
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8-bit to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
– Peripherals Can Be Deactivated Individually
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
2.3V to 3.6V or 1.8V Core Supply Voltage
Includes Power Supervisor
1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
4 Kbytes Battery Backup Memory
8 mm
×
8 mm 56 Pin QFN56 Package
Pb-free, RoHS-compliant, Green
•
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•
GPS Baseband
Processor
SuperSense
ATR0625
Preliminary
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Rev. 4925A–GPS–02/06
1. Description
The GPS baseband processor ATR0625 includes a 16-channel GPS correlator and is based
on the ARM7TDMI
®
processor core.
This processor has a high-performance 32-bit RISC architecture and very low power con-
sumption. In addition, a large number of internally banked registers result in very fast
exception handling, making the device ideal for real-time control applications. The ATR0625
has two USART and an USB device port. This port is compliant with the Universal Serial Bus
(USB) V2.0 full-speed device specification.
The ATR0625 includes full GPS SuperSense
™
firmware, licensed from u-blox AG, which per-
forms the basic GPS operation, including tracking, acquisition, navigation and position data
output. For normal PVT (Position/Velocity/Time) applications, there is no need for off-chip
Flash memory or ROM. The firmware supports the possibility to store the configuration set-
tings in an optional external EEPROM. For customer-specific applications, a Software
Development Kit is available.
The ATR0625 is manufactured using Atmel’s high-density CMOS technology. By combining
the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator, and a
wide range of peripheral functions on a monolithic chip, the ATR0625 provides a highly flexible
and cost-effective solution for GPS applications.
2
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
Figure 1-1.
ATR0625 Block Diagram
GPS
Accelerator
GPS
Correlators
XT_IN
XT_OUT
Advanced
Power
Manage-
ment
Controller
SRAM
RTC
NSHDN
NSLEEP
RF_ON
CLK23
SIGLO0
SIGHI0
SMD
Generator
P0/NANTSHORT
P14/NAADET1
P25/NAADET0
P20/TIMEPULSE
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
P9/EXTINT0
P2/BOOT_MODE
P30/AGCOUT0
P8/STATUSLED
PIO2
Controller
APB
SPI
Timer
Counter
P15/ANTON
USART2
Special
Function
P21/TXD2
PIO2
P22/RXD2
PIO2
Advanced
Interrupt
Controller
USART1
P18/TXD1
P31/RXD1
USB
Transceiver
Watchdog
P16/NEEPROM
USB_DP
USB_DM
B
R
I
D
G
E
USB
ASB
Interface to
Off-Chip
Memory
(EBI)
ARM7TDMI
Embedded
ICE
DBG_EN
NTRST
TDI
TDO
TCK
TMS
JTAG
SRAM
128K
ROM
384K
PDC2
Reset
Controller
Power
Supply
Manager
VBAT18
VBAT
LDOBAT_IN
LDO_OUT
LDO_IN
LDO_EN
NRESET
3
4925A–GPS–02/06
2. Architectural Overview
2.1
Description
The ATR0625 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-
faces the processor with the on-chip 32-bit memories. The APB is designed for accesses to
on-chip peripherals and is optimized for low power consumption. The AMBA
™
Bridge provides
an interface between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip
USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most
importantly, the PDC2 removes the processor interrupt handling overhead and significantly
reduces the number of clock cycles required for a data transfer. It can transfer up to 64K con-
tiguous bytes without reprogramming the starting address. As a result, the performance of the
microcontroller is increased and the power consumption reduced.
The ATR0625 peripherals are designed to be easily programmable with a minimum number of
instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of
the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address
space.) The peripheral base address is the lowest address of its memory space. The periph-
eral register set is composed of control, mode, data, status, and interrupt registers.
To maximize the efficiency of bit manipulation, frequently written registers are mapped into
three memory locations. The first address is used to set the individual register bits, the second
resets the bits, and the third address reads the value stored in the register. A bit can be set or
reset by writing a “1” to the corresponding position at the appropriate address. Writing a “0”
has no effect. Individual bits can thus be modified without having to use costly read-modify-
write and complex bit-manipulation instructions.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O
(PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin
or generate an interrupt on a signal change. After reset, the user must carefully program the
PIO2 Controller in order to define which peripheral signals are connected with off-chip logic.
The ARM7TDMI
®
processor operates in little-endian mode on the ATR0625 GPS Baseband.
The processor's internal architecture and the ARM
®
and Thumb
®
instruction sets are
described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are
described in detail in the ATR0625 full datasheet. The electrical and mechanical characteris-
tics are also documented in the ATR0625 full datasheet.
The ARM standard In-Circuit Emulator (ICE) debug interface is supported via the JTAG/ICE
port of the ATR0625.
For features of the ROM firmware, refer to the software documentation available from u-blox
AG, Switzerland.
4
ATR0625 [Preliminary]
4925A–GPS–02/06
ATR0625 [Preliminary]
3. Pin Configuration
3.1
Pinout
Pinout QFN56 (Top View)
Figure 3-1.
42
43
29
28
ATR0625
56
1
Table 3-1.
Pin Name
CLK23
DBG_EN
GND
LDOBAT_IN
LDO_EN
LDO_IN
LDO_OUT
NRESET
NSHDN
NSLEEP
NTRST
P0
P1
P2
P8
P9
P12
P13
Notes:
15
14
ATR0625 Pinout
QFN56
37
8
(2)
Pin
Type
IN
IN
IN
IN
IN
IN
OUT
I/O
OUT
OUT
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pull Resistor
(Reset Value)
(1)
PD
PIO Bank A
Firmware Label
I
O
I
PIO Bank B
O
21
25
20
19
41
26
24
13
40
47
46
48
29
49
32
Open Drain PU
PD
PD
Configurable (PD)
Configurable (PD)
Configurable (PD)
PU
Configurable (PU)
PU
NANTSHORT
GPSMODE0
BOOT_MODE
STATUSLED
EXTINT0
GPSMODE2
GPSMODE3
EXTINT1
EXTINT0
NPCS2
AGCOUT1
“0”
“0”
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. Ground plane
3. VBAT18 represent the internal power supply of the backup power domain, see section
“Power Supply” on page 17.
4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section
“Power Supply” on page 17.
5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP, see section
“Power Supply” on page
17.
For operation of the USB interface, supply of 3.0V to 3.6V is required.
6. This pin is not connected
5
4925A–GPS–02/06
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