P
RELIMINARY
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
1
Z86E02 SL1925
CMOS Z8
®
OTP M
ICROCONTROLLER
FEATURES
Part
Number
Z86E02
* General-Purpose
s
s
s
1
ROM
(Kilobytes)
0.5
RAM*
(Bytes)
61
Speed
(MHz)
8
Program Options:
– Low Noise
–
–
–
–
–
ROM Protect
Auto Latch
Permanent Watch-Dog Timer (WDT)
EPROM/TEST Mode Disable
RC Oscillator
18-Pin DIP and SOIC Packages
3.5V to 5.5V Operating Range @ 0
°
C to +70
°
C
4.5V to 5.5V Operating Range @ -40
°
C to +105
°
C
14 Input / Output Lines
Five Vectored, Prioritized Interrupts with Programmable
Polarity
Two Analog Comparators
WDT/Power-On Reset (POR)
s
s
s
s
One Programmable 8-Bit Counter/Timer, with
6-Bit Programmable Prescaler
On-Chip Oscillator that Accepts RC, XTAL, Ceramic
Resonance, LC, or External Clock
Clock-Free WDT Reset
Low-Power Consumption (50 mw)
Fast Instruction Pointer (1.5
µ
s @ 8 MHz)
s
s
s
s
s
GENERAL DESCRIPTION
Zilog's Z86E02 Microcontroller (MCU) is a One-Time Pro-
grammable (OTP) member of the Z8 single-chip microcon-
troller family which allow easy software development, de-
bug, prototyping, and small production runs not
economically desirable with masked ROM versions.
For applications demanding powerful I/O capabilities, the
Z86E02's dedicated input and output lines are grouped into
three ports, and are configurable under software control to
provide timing, status signals, or parallel I/O.
An on-chip counter/timer, with a large number of user se-
lectable modes, offload the system of administering real-
time tasks such as counting/timing and I/O data communi-
cations.
Note:
All Signals with a preceding front slash, “/”, are
active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE
is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V
CC
Device
V
DD
V
SS
GND
CP97DZ83501
PRELIMINARY
1
Z86E02 SL1925
CMOS Z8® OTP Microcontroller
Zilog
GENERAL DESCRIPTION
(Continued)
Input
Vcc
GND
XTAL
Port 3
Machine
Timing & Inst.
Control
Counter/
Timer
ALU
Interrupt
Control
FLAG
OTP
Two Analog
Comparators
Register
Pointer
General-Purpose
Register File
Program
Counter
Port 2
Port 0
I/O
(Bit Programmable)
I/O
Figure 1. Functional Block Diagram
2
PRELIMINARY
CP97DZ83501
Zilog
Z86E02 SL1925
CMOS Z8® OTP Microcontroller
D7-D0
Address MUX
Z8 MCU
A10-A0
1
Data MUX
Z8 PORT2
D7-D0
/OE
P31
A10-A0
0.5K
EPROM
D7-D0
ROM PROT
Low Noise
Address
Counter
A10-A0
3 Bits
PGM
Mode Logic
Clear Clock
P00 P01
EPM /CE /PGM
P32 XT1 P02
VPP
P33
Figure 2. EPROM Programming Mode Block Diagram
CP97DZ83501
PRELIMINARY
3
Z86E02 SL1925
CMOS Z8® OTP Microcontroller
Zilog
PIN DESCRIPTION
D4
D5
D6
D7
VCC
N/C
/CE
/OE
EPM
1
18
DIP 18 - Pin
9
10
D3
D2
D1
D0
GND
/PGM
CLOCK
CLEAR
VPP
P24
P25
P26
P27
VCC
XTAL2
XTAL1
P31
P32
1
18
DIP 18 - Pin
9
10
P23
P22
P21
P20
GND
P02
P01
P00
P33
Figure 3. 18-Pin EPROM Mode Configuration
Table 1. 18-Pin DIP Pin Identification
EPROM Programming Mode
Pin #
Symbol
Function
1–4
5
6
7
8
9
10
11
12
13
14
15–18
D4–D7
V
CC
N/C
/CE
/OE
EPM
V
PP
Clear
Clock
/PGM
GND
D3–D0
Data 4, 5, 6, 7
Power Supply
No Connection
Chip Enable
Output Enable
EPROM Prog Mode
Prog Voltage
Clear Clock
Address
Prog Mode
Ground
Data 0,1, 2, 3
Figure 4. 18-Pin DIP/SOIC Standard Mode
Configuration
Table 2. 18-Pin DIP/SOIC Pin Identification
Direction
In/Output
Standard Mode
Pin #
Symbol
1–4
5
P24–P27
V
cc
XTAL2
XTAL1
P31
P32
P33
P00–P02
GND
P20–P23
Function
Port 2, Pins 4,5,6,7
Power Supply
Crystal Osc. Clock
Crystal Osc. Clock
Port 3, Pin 1, AN1
Port 3, Pin 2, AN2
Port 3, Pin 3, REF
Port 0, Pins 0,1,2
Ground
Port 2, Pins 0,1,2,3
Direction
In/Output
Output
Input
Input
Input
Input
In/Output
In/Output
Input
Input
Input
Input
Input
Input
Input
In/Output
6
7
8
9
10
11–13
14
15–18
4
PRELIMINARY
CP97DZ83501
Zilog
Z86E02 SL1925
CMOS Z8® OTP Microcontroller
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper-
ational sections of these specifications is not implied. Ex-
posure to absolute maximum rating conditions for an ex-
tended period may affect device reliability. Total power
Parameter
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to V
SS
Voltage on V
DD
Pin with Respect to V
SS
Voltage on Pins 7, 8, 9, 10 with Respect to V
SS
Total Power Dissipation
Maximum Allowable Current out of V
SS
Maximum Allowable Current into V
DD
Maximum Allowable Current into an Input Pin
Maximum Allowable Current into an Open-Drain Pin
Maximum Allowable Output Current Sinked by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
–600
–600
dissipation should not exceed 462 mW for the package.
Power dissipation is calculated as follows:
Total Power Dissipation = V
DD
x [I
DD
- (sum of I
OH
)]
+ sum of [(V
DD
- V
OH
) x I
OH
]
+ sum of (V
0L
x I
0L
)
Min
–40
–65
–0.7
–0.3
–0.6
Max
+105
+150
+12
+7
V
DD
+1
462
240
240
+600
+600
20
20
Units
C
C
V
V
V
mW
mA
mA
µ
A
µ
A
mA
mA
3
4
2
Note
1
1
Notes:
[1] This applies to all pins except where otherwise noted. Maximum current into pin must be
±
600
µ
A.
[2] There is no input protection diode from pin to V (not applicable to EPROM Mode).
[3] This excludes Pin 6 and Pin 7.
[4] Device pin is not at an output Low state.
DD
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Fig-
ure 5).
From Output
Under Test
150 pF
Figure 5. Test Load Diagram
CP97DZ83501
PRELIMINARY
5
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