Features
•
64-megabit (4M x 16) Flash Memory
•
2.7V - 3.6V Read/Write
•
High Performance
– Asynchronous Access Time – 70 ns
– Page Mode Read Time – 20 ns
Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 200 ms
Four Plane Organization, Permitting Concurrent Read in Any of the Three Planes not
Being Programmed/Erased
– Memory Plane A: 16M Memory Including Eight 4K Word Sectors
– Memory Plane B: 16M Memory Consisting of 32K Word Sectors
– Memory Plane C: 16M Memory Consisting of 32K Word Sectors
– Memory Plane D: 16M Memory Consisting of 32K Word Sectors
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 35 µA Standby
2.2V I/O Option Reduces Overall System Power
VPP Pin for Write Protection and Accelerated Program/Erase Operations
Reset Input for Device Initialization
CBGA Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
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•
•
•
64-megabit
(4M x 16)
Page Mode
2.7-volt Flash
Memory
AT49BV6416C
AT49BV6416CT
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•
•
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•
1. Description
The AT49BV6416C(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided
into multiple sectors and planes for erase operations. The device can be read or
reprogrammed off a single 2.7V power supply, making it ideally suited for In-System
programming. The device can operate in the asynchronous or page read mode.
The AT49BV6416C(T) is divided into four memory planes. A read operation can occur
in any of the three planes which is not being programmed or erased. This concurrent
operation allows improved system performance by not requiring the system to wait for
a program or erase operation to complete before a read is performed. To further
increase the flexibility of the device, it contains an Erase Suspend and Program Sus-
pend feature. This feature will put the erase or program on hold for any amount of time
and let the user read data from or program data to any of the remaining sectors. There
is no reason to suspend the erase or program operation if the data to be read is in
another memory plane.
The VPP pin provides data protection and faster programming times. When the V
PP
input is below 0.7V, the program and erase functions are inhibited. When V
PP
is at
1.65V or above, normal program and erase operations can be performed. With V
PP
at
10.0V, the program (Dual-word Program command) operation is accelerated.
3465C–FLASH–07/05
2. Pin Configurations
Pin Name
I/O0 - I/O15
A0 - A21
CE
OE
WE
Reset
WP
VPP
VCCQ
Pin Function
Data Inputs/Outputs
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Write Protect
Write Protection and Power Supply for Accelerated Program/Erase Operations
Output Power Supply
2.1
48-ball CBGA – Top View
1
A
A13
A11
A10
A12
A8
WE
A9
VPP
RST
A21
WP
A18
A20
A19
A17
A6
I/O8
I/O9
A7
A5
A3
CE
I/O0
A4
A2
A1
A0
GND
OE
2
3
4
5
6
7
8
B
A14
C
A15
D
A16 I/O14 I/O5 I/O11 I/O2
E
VCCQ I/O15 I/O6 I/O12 I/O3
F
GND
I/O7 I/O13 I/O4
VCC I/O10 I/O1
2
AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
3. Device Operation
3.1
Command Sequences
When the device is first powered on, it will be in the read mode. Command sequences are used
to place the device in other operating modes such as program and erase. The command
sequences are written by applying a low pulse on the WE input with CE low and OE high or by
applying a low-going pulse on the CE input with WE low and OE high. The address is latched on
the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or the CE
pulse, whichever occurs first. The addresses used in the command sequences are not affected
by entering the command sequences.
3.2
Asynchronous Read
The AT49BV6416C(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins are asserted on the out-
puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
3.3
Page Read
The page read operation of the device is controlled by CE and OE inputs. The page size is four
words. The first word access of the page read is the same as the asynchronous read. The first
word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1
will result in subsequent reads within the page being output at a speed of 20 ns. See the
“Page
Read Cycle Waveform” on page 24.
3.4
Reset
A Reset input pin is provided to ease some system applications. When Reset is at a logic high
level, the device is in its standard operating mode. A low level on the Reset pin halts the present
device operation and puts the outputs of the device in a high-impedance state. When a high
level is reasserted on the Reset pin, the device returns to read mode.
3.5
Erase
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a
logical “1”. The entire memory can be erased by using the Chip Erase command or individual
planes can be erased by using the Plane Erase command or individual sectors can be erased by
using the Sector Erase command.
3.5.1
Chip Erase
Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the
last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset
during chip erase will stop the erase, but the data will be of an unknown state.
3.5.2
Plane Erase
As an alternative to a full Chip Erase, the device is organized into four planes that can be individ-
ually erased. The Plane Erase command is a two-bus cycle operation. The plane whose address
is valid at the second rising edge of WE will be erased. The Plane Erase command does not
alter the data in the protected sectors.
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3465C–FLASH–07/05
3.5.3
Sector Erase
The device is organized into multiple sectors that can be individually erased. The Sector Erase
command is a two-bus cycle operation. The sector whose address is valid at the second rising
edge of WE will be erased provided the given sector has not been protected.
3.6
Word Programming
The device is programmed on a word-by-word basis. Programming is accomplished via the
internal device command register and is a two-bus cycle operation. The programming address
and data are latched in the second cycle. The device will automatically generate the required
internal programming pulses. Please note that a “0” cannot be programmed back to a “1”; only
erase operations can convert “0”s to “1”s.
3.7
Flexible Sector Protection
The AT49BV6416C(T) offers two sector protection modes, the Softlock and the Hardlock. The
Softlock mode is optimized as sector protection for sectors whose content changes frequently.
The Hardlock protection mode is recommended for sectors whose content changes infrequently.
Once either of these two modes is enabled, the contents of the selected sector is read-only and
cannot be erased or programmed. Each sector can be independently programmed for either the
Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Soft-
lock protection mode enabled.
3.7.1
Softlock And Unlock
The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to
the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To
enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the
selected sector.
Hardlock And Write Protect (WP)
The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin.
The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock soft-
ware command to the selected sector. The state of the Write Protect pin affects whether the
Hardlock protection mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be
unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector can be
unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
3.7.2
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AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
Table 3-1.
Hardlock and Softlock Protection Configurations in Conjunction with WP
Hard-
lock
0
0
Soft-
lock
0
1
Erase/
Prog
Allowed?
Yes
No
V
PP
V
CC
V
CC
WP
0
0
Comments
No sector is locked
Sector is Softlocked. The
Unlock command can unlock
the sector.
Hardlock protection mode is
enabled. The sector cannot be
unlocked.
No sector is locked.
Sector is Softlocked. The
Unlock command can unlock
the sector.
Hardlock protection mode is
overridden and the sector is
not locked.
Hardlock protection mode is
overridden and the sector can
be unlocked via the Unlock
command.
Erase and Program Operations
cannot be performed.
V
CC
V
CC
V
CC
0
1
1
1
0
0
1
0
1
No
Yes
No
V
CC
1
1
0
Yes
V
CC
1
1
1
No
V
IL
x
x
x
No
Figure 3-1.
Sector Locking State Diagram
UNLOCKED
LOCKED
[000]
A
C
B
[001]
WP = V
IL
= 0
C
[011]
Power-Up/Reset
Default
Hardlocked
[110]
A
C
A
B
B
[111]
Hardlocked is disabled by
WP = V
IH
WP = V
IH
= 1
C
Power-Up/Reset
Default
[100]
[101]
A
= Unlock Command
B
= Softlock Command
C
= Hardlock Command
Note:
1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector
is defined by the state of WP and the two bits of the sector-lock status D[1:0].
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3465C–FLASH–07/05
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