DM9000A
Ethernet Controller with General Processor Interface
DAVICOM Semiconductor, Inc.
DM9000A
Ethernet Controller
with General Processor Interface
DATA SHEET
Preliminary
Version: DM9000A-DS-P03
Apr. 21, 2005
Preliminary
Version: DM9000A-DS-P03
Apr. 21, 2005
1
DM9000A
Ethernet Controller with General Processor Interface
Content
1. General Description
………………………………………………………….…………………..………………6
2. Block Diagram
…………………………………………………………………………….………………………6
3. Feature
…………………………………………………………………………………….…….……………………7
4. Pin Configuration
…………………………………………………………………………………………………8
4.1 Pin Configuration I: 16-bit mode……..………………………….……..……………………………………………8
4.2 Pin Configuration II: 8-bit mode…………..…………………………………………………………………………9
5. Pin Description
……………………………………………………………………………………………………10
5.1 Processor Interface…..…………………………………………………………………………...…………………10
5.1.1 8-bit mode …….………………………………………………………………..…………………………………10
5.2 EEPROM Interface……………………………………………………………………………………………….…11
5.3 Clock Interface………………………………………………………………………………………………………11
5.4 LED Interface……………………………………………………….………….……………………………………11
5.5 10/100 PHY/Fiber………………………………………………….…..……………………………………………11
5.6 Miscellaneous………………………………………….…………………….………………………………………12
5.7 Power Pins………………………………………………………………………………………………..…………12
5.8 strap pins table ……………………………………………………………………………….…….…..……….…..12
6. Vendor Control and Status Register Set
………………………………………………..…………………13
6.1Network Control Register (00H)…………………………………………………………………....……..…………14
6.2 Network Status Register (01H)…………………………………………………………….……….…….…………15
6.3 TX Control Register (02H)………………………………………………………………………...….…….………15
6.4 TX Status Register I ( 03H ) for packet index I………………………….………………………….………………15
6.5 TX Status Register II ( 04H ) for packet index I I…………………….………..………………….…..……………16
6.6 RX Control Register ( 05H )……………..……………………………………..……..………….…………………16
6.7 RX Status Register ( 06H )………………..…………………………………….……...……….….……….………16
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
2
DM9000A
Ethernet Controller with General Processor Interface
6.8 Receive Overflow Counter Register ( 07H )……………………………………..…………….…………..………17
6.9 Back Pressure Threshold Register (08H)…………………………………………………….. .……….……….…17
6.10 Flow Control Threshold Register ( 09H )…………………………………………………….……….……….…17
6.11 RX/TX Flow Control Register ( 0AH )……………………………………….…………….…..……………..…18
6.12 EEPROM & PHY Control Register ( 0BH )………………………………….…………….……………………18
6.13 EEPROM & PHY Address Register ( 0CH )…………………………………..………….………..……………18
6.14 EEPROM & PHY Data Register (0DH~0EH) ………………………………….……….………………………18
6.15 Wake Up Control Register ( 0FH )……………………………………………….…….…………..……………19
6.16 Physical Address Register ( 10H~15H )………………………………………….…….………….………….…19
6.17 Multicast Address Register ( 16H~1DH ) ……………………………………….…….…………...……………19
6.18 General purpose control Register
( 1EH )……………………………………….….……………….…………19
6.19 General purpose Register ( 1FH )………………………………………………….….…………………………20
6.20 TX SRAM Read Pointer Address Register (22H~23H)……………………………..……..……………………20
6.21 RX SRAM Write Pointer Address Register (24H~25H)……………………………..…………….……………20
6.22 Vendor ID Register (28H~29H)………………………………………………………..………………..………20
6.23 Product ID Register (2AH~2BH)………………………………………………………..………………………20
6.24Chip Revision Register (2CH)………………………………………………………….…….…….…………….20
6.25Transmit Control Register 2 ( 2DH ) ……………………………………………………..….…..………………20
6.26 Operation Test Control Register ( 2EH )…………………..………………………….……….….…..…………21
6.27 Special Mode Control Register ( 2FH )……………………...…………………………………….….…………21
6.28Early Transmit Control/Status Register ( 30H )…………………………………………………….……………22
6.29Check Sum Control Register ( 31H )……………………………………………………………….….…………22
6.30 Receive Check Sum Control Status Register ( 32H )…………………………………………….………………22
6.31 Memory Data Pre-Fetch Read Command without Address Increment (F0H)…………………….….….………23
6.32 Memory Data Read Command without Address Increment Register (F1H)………………..……….……..……23
6.33 Memory Data Read Command with Address Increment Register (F2H) ………………………….…….………23
6.34 Memory Data Read_address Register (F4H~F5H)………………………………………………………….……23
6.35 Memory Data Write Command without Address Increment Register (F6H)……………………………….……23
6.36 Memory data write command with address increment Register (F8H)…………….……………………….……23
6.37 Memory data write_address Register (FAH~FBH)………………………………….……………..……….……23
6.38 TX Packet Length Register (FCH~FDH)……………………………………………………………..…….……23
6.39 Interrupt Status Register (FEH)……………………………………………………………….…………….……24
6.40 Interrupt Mask Register (FFH)……………………………………………………….……….…………….……24
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
3
DM9000A
Ethernet Controller with General Processor Interface
7. EEPROM Format
…………………………………………………………….………..……..…………………25
8. PHY Register Description
……………………………………..………………………….……………………26
8.1 Basic Mode Control Register (BMCR) - 00…………………………………………….…….……………………27
8.2 Basic Mode Status Register (BMSR) - 01……………………………………………….…………………………28
8.3 PHY ID Identifier Register #1 (PHYIDR1) - 02…………………………………..………………….……………29
8.4 PHY ID Identifier Register #2 (PHYIDR2) - 03………………………………….………………….…….………30
8.5 Auto-negotiation Advertisement Register (ANAR) - 04………………………………..…………….……………31
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - 05…………………………………….……………32
8.7 Auto-negotiation Expansion Register (ANER)- 06………………………………………..…………….…………33
8.8 DAVICOM Specified Configuration Register (DSCR) -16……………………………………….…….…………33
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) -17 ……………………………….…………35
8.10 10Base-T Configuration / Status (10BTCSR) - 18………………………………………………….….…………36
8.11 Power Down Control Register (PWDOR) - 19…………………………………………….…………..…………37
8.12(Specified config) Register – 20…………………………………………………………………….…..…………37
9. Functional Description
……………………………………………………………………………..….………39
9.1 Host Interface…………………………………………………………………………………………..…...………39
9.2 Direct Memory Access Control ……………………………………………………….…………….….….………39
9.3 Packet Transmission…………………………………………………………………………………….….………39
9.4 Packet Reception……………………………………………………………………………..…………….………39
9.5 100Base-TX Operation………………………………………………………………………………….….………40
9.6 100Base-TX Receiver…………………………………………………………….…………………….…..………42
9.7 10Base-T Operation………………………………………………………………….……………….….…………43
9.8 Collision Detection…………………………………………………………………..…………………..…………43
9.9 Carrier Sense………………………………………………………………………………….………….…………43
9.10 Auto-Negotiation………………………………………………………………………………..…………………43
9.11 Power Reduced Mode……………………………………………………………………..………………………44
10. DC and AC Electrical Characteristics
………………………..…………………………….…….………45
10.1 Absolute Maximum Ratings(25℃)…………………….……………………………………………….…………45
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
4
DM9000A
Ethernet Controller with General Processor Interface
10.1.1 Operating Conditions………………………………………………………………………………..………..…45
10.2 DC Electrical Characteristics (VDD = 3.3V)……………………………….…………………………..…………45
10.3 AC Electrical Characteristics & Timing Waveform……………………………………………………..…..……46
10.3.1 TP Interface…………………………………………………………………………………………..…………46
10.3.2 Oscillator/Crystal Timing……………………………………………………………………………….………46
10.3.3 Processor Register Read Timing…………………………………………………………………….….………46
10.3.4 Processor Register Write Timing………………………………………………………………….…….………47
10.3.5 EEPROM Interface Timing………………………………………………………………………….……..……48
11. Application Notes
………………………………………………………………………………….……………49
11.1 Network Interface Signal Routing………………………………………………………………….………………49
11.2 10Base-T/100Base-TX (Auto MDIX Application)…….…………………………………………….….…………49
11.3 10Base-T/100Base-TX (Non Auto MDIX Application)…………………………………………….…..…………50
11.4 Power Decoupling Capacitors…………………………………………………………..…………….……………51
11.5 Ground Plane Layout………………………………………………………………………………….……………52
11.6 Power Plane Partitioning……………………………………………………………………………………………53
11.7 Magnetics Selection Guide………………………………………………………………………………….………54
11.8 Crystal Selection Guide…………………………………………………………………………..…………………54
12. Package Information
………………………………………………………………………….……………..55
13. Ordering Information
………………………………………………………………………….……….……56
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
5
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