MM74HCT273 Octal D-Type Flip-Flop with Clear
February 1984
Revised May 2005
MM74HCT273
Octal D-Type Flip-Flop with Clear
General Description
The MM74HCT273 utilizes advanced silicon-gate CMOS
technology. It has an input threshold and output drive simi-
lar to LS-TTL with the low standby power of CMOS.
These positive edge-triggered flip-flops have a common
clock and clear-independent Q outputs. Data on a D input,
having the specified set-up and hold time, is transferred to
the corresponding Q output on the positive-going transition
of the clock pulse. The asynchronous clear forces all out-
puts LOW when it is LOW.
All inputs to this device are protected from damage due to
electrostatic discharge by diodes to V
CC
and ground.
MM74HCT devices are intended to interface TTL and
NMOS components to CMOS components. These parts
can be used as plug-in replacements to reduce system
power consumption in existing designs.
Features
s
Typical propagation delay: 20 ns
s
Low quiescent current: 80
P
A maximum (74HCT series)
s
Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
MM74HCT273WM
MM74HCT273SJ
MM74HCT273MTC
MM74HCT273N
Package
Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
© 2005 Fairchild Semiconductor Corporation
DS005760
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MM74HCT273
Truth Table
(Each Flip-Flop)
Inputs
Clear
L
H
H
H
H HIGH Level (steady-state)
L LOW Level (steady-state)
X Don’t Care
n
Transition from LOW-to-HIGH level
Q0 The level of Q before the indicated steady-state input
conditions were established.
Outputs
D
X
H
L
X
Q
L
H
L
Q0
Clock
X
n
n
L
Logic Diagram
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2
MM74HCT273
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per Pin (I
OUT
)
DC V
CC
or GND Current, per Pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
q
C
600 mW
500 mW
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
)
500
ns
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power dissipation temperature derating—plastic “N” package:
12
mW/
q
C from 65
q
C to 85
q
C.
0.5V to
7.0V
1.5V to V
CC
1.5V
0.5V to V
CC
0.5V
r
20 mA
r
25 mA
r
50 mA
65
q
C to
150
q
C
Max
5.5
V
CC
Units
V
V
4.5
0
40
85
q
C
DC Electrical Characteristics
V
CC
5V
r
10% unless otherwise specified
Parameter
Minimum HIGH Level
Input Voltage
V
IL
V
OH
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
V
OL
Minimum LOW Level
Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
V
IN
V
IN
I
OUT
V
IN
V
IH
or V
IL
20
P
A
4.0 mA, V
CC
4.8 mA, V
CC
V
IH
or V
IL
20
P
A
4.0 mA, V
CC
4.8 mA, V
CC
V
CC
or GND,
V
CC
or GND
0
P
A
2.4V or 0.5V (Note 4)
0.6
0.8
0.9
mA
4.5V
5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
4.5V
5.5V
V
CC
4.2
5.2
V
CC
0.1
3.98
4.98
V
CC
0.1
3.84
4.84
V
CC
0.1
3.7
4.7
V
V
V
0.8
0.8
0.8
V
Conditions
T
A
Typ
2.0
25
q
C
T
A
Symbol
V
IH
40
q
C to 85
q
C T
A
55
q
C to 125
q
C
Guaranteed Limits
2.0
2.0
Units
V
r
0.1
8
r
1.0
80
r
1.0
160
P
A
P
A
V
IH
or V
IL
Note 4:
Measured per pin, all other inputs held at V
CC
or GND.
3
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MM74HCT273
AC Electrical Characteristics
V
CC
5V, T
A
25
q
C, C
L
15 pF, t
r
t
f
6 ns
Conditions
Typ
68
18
21
Guaranteed
Limits
30
30
30
5
20
5
16
Units
MHz
ns
ns
ns
ns
ns
ns
Symbol
f
MAX
t
PHL
, t
PLH
t
PHL
, t
PLH
t
REM
t
S
t
H
t
W
Parameter
Maximum Operating Frequency
Maximum Propagation Delay from Clock to Q
Maximum Propagation Delay from Clear to Q
Minimum Removal Time, Clear to Clock
Minimum Set-Up Time D to Clock
Minimum Hold Time Clock to D
Minimum Pulse Width Clock or Clear
1
6
3
10
AC Electrical Characteristics
V
CC
5.0V
r
10%, C
L
50 pF, t
r
t
f
6 ns unless otherwise specified
Conditions
T
A
Typ
68
22
25
25
q
C
27
37
35
5
20
5
16
500
11
(Per Flip-Flop)
50
6
10
10
10
15
T
A
Symbol
Parameter
40
q
C to 85
q
C T
A
55
q
C to 125
q
C Units
Guaranteed Limits
21
46
44
6
25
5
25
500
19
18
56
52
7
30
5
30
500
22
MHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
f
MAX
Maximum Operating
Frequency
t
PHL
, t
PLH
Maximum Propagation
Delay from Clock to Q
t
PHL
, t
PLH
Maximum Propagation
Delay from Clear to Q
t
REM
t
S
t
H
t
W
t
r
, t
f
Minimum Removal
Time Clear to Clock
Minimum Set-Up Time
D to Clock
Minimum Hold Time
Clock to D
Minimum Pulse Width
Clock or Clear
Maximum Input Rise
and Fall Time, Clock
t
THL
, t
TLH
Maximum Output Rise
and Fall Time
C
PD
C
IN
Power Dissipation
Capacitance (Note 5)
Maximum Input
Capacitance
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
I
S
C
PD
V
CC
f
I
CC
.
2
1
6
3
10
C
PD
V
CC2
f
I
CC
V
CC
, and the no load dynamic current consumption,
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4
MM74HCT273
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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