PI6C10804
1.8V/2.5V, 250MHz, 1:4 Networking Clock Buffer
Features
• High-speed, low-noise, non-inverting 1:4 buffer
• Maximum Frequency up to 250 MHz
• Low output skew < 150ps
• Low propagation delay < 3.0ns
• 1.8V or 2.5V supply voltage
• Packages (Pb-free & Green available):
-8-pin SOIC (W)
Description
The PI6C10804 is a 1.8V or 2.5V high-speed, low-noise
1:4 non-inverting clock buffer. The key goal in designing the
PI6C10804 is to target networking applications that require low-
skew, low-jitter, and high-frequency clock distribution.
Providing output-to-output skew as low as 150ps, the PI6C10804
is an ideal clock distribution device for synchronous systems. De-
signing synchronous networking systems requires a tight level of
skew from a large number of outputs.
Block Diagram
Pin Configuration
½½
½½½½½½
½
½
½
½
½
½
½
½
½½
½½½
½½½
½½½½
½½½½
½½½½
½½½½
½½½½½
½½½½½½
½½½½
½½½½
½½½½
Pin Description
Pin Name
BUF_IN
CLK [0:3]
GND
V
DD
OE
06-0035
Description
Input
Outputs
Ground
Power
Output Enable
PS8822B
04/03/06
1
PI6C10804
1.8V/2.5V, 250MHz, 1:4 Networking Clock Buffer
2.5V Absolute Maximum Ratings
(Above which the useful life may be impaired. For user guidelines only, not tested.)
Storage Temperature...........................................................–65°C to +150°C
V
DD
Voltage ..........................................................................–0.5V to +3.6V
Output Voltage (max. 3.6V) .......................................... –0.5V to V
DD
+0.5V
Input Voltage (max 3.6V).............................................. –0.5V to V
DD
+0.5V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
2.5V DC Characteristics
(Over Operating Range: V
DD
= 2.5V ± 0.2V, T
A
= -40° to 85°C)
Parameters Description
V
DD
V
IH
V
IL
I
I
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
Logic HIGH level
Logic LOW level
V
DD
= Max, Vin = V
DD
or GND
I/O pins
non I/O pins
I
OH
= -1mA
V
OH
Output High Voltage
V
DD
= Min., V
IN
= V
IH
or V
IL
I
OH
= -2mA
I
OH
= -8mA
I
OL
= 1mA
V
OL
Output LOW Voltage
V
DD
= Min., V
IN
- V
IH
or V
IL
I
OL
= 2mA
I
OL
= 8mA
2.0
1.7
1.5
Test Conditions
(1)
Min.
2.3
1.7
-0.3
Typ.
(2)
2.5
Max.
2.7
3.6
0.7
15
5
Units
V
V
µA
V
0.4
0.7
0.7
V
Notes:
1. For Max. or Min. conditions, use appropriate operating range values.
2. Typical values are at V
CC
= 2.5V, +25°C ambient and maximum loading.
2.5V AC Characteristics
(Over Operating Range: V
DD
= 2.5V ± 0.2V, T
A
= -40° to 85°C)
Parameters
F
IN
t
R
/t
F
t
PLH,
t
PHL(2)
t
SK(O)(3)
t
SK(P)(3)
t
SK(T)(3)
tdc_in
tdc_out
Input Frequency
CLKn Rise/Fall Time
Propagation Delay BUF_IN to CLKn
Output to Output Skew between any two
outputs of the same device @ same transition
Pulse Skew between opposite transitions
(t
PHL
-t
PLH
) of the same output
Part to Part Skew between two identical out-
puts of different parts on the same board
(4)
Duty Cycle In @ 1ns edge rate
Duty Cycle Out
C
L
= 5pF, 125 MHz
Outputs are measured
@ Vdd/2
40
40
20% to 80%
1.0
1.5
100
100
Description
Test Conditions
(1)
Min.
0
Typ
Max.
250
1.0
2.0
150
200
300
60
60
%
ps
Units
MHz
ns
ns
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew measured at worse cast temperature (max. temp).
4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
06-0035
2
PS8822B
04/03/06
PI6C10804
1.8V/2.5V, 250MHz, 1:4 Networking Clock Buffer
1.8V Absolute Maximum Ratings
(Above which the useful life may be impaired. For user guidelines only, not tested.)
Storage Temperature...........................................................–65°C to +150°C
V
DD
Voltage ..........................................................................–0.5V to +2.5V
Output Voltage (max 2.5V) .......................................... –0.5V to V
DD
+0.5V
Input Voltage (max 2.5V) ............................................. –0.5V to V
DD
+0.5V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
1.8V DC Characteristics
(Over Operating Range: V
DD
= 1.8V ± 0.15V, T
A
= -40° to 85°C)
Param-
eters
V
DD
V
IH
V
IL
I
I
V
OH
V
OL
Description
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
(3)
Output High Voltage
Output LOW Voltage
Logic HIGH level
Logic LOW level
V
DD
= Max,
Vin = V
DD
or GND
V
DD
= Min., V
IN
= V
IH
or V
IL
V
DD
= Min., V
IN
- V
IH
or V
IL
I/O pins
non I/O pins
I
OH
= -2mA
I
OH
= -8mA
I
OL
= 2mA
I
OL
= -8mA
1.3
1.2
0.45
0.45
V
Test Conditions
(1)
Min.
1.65
0.65*Vdd
-0.3
Typ.
(2)
1.8
Max.
1.95
2.7
0.35*Vdd
15
5
Units
V
V
µA
Notes:
1. For Max. or Min. conditions, use appropriate operating Vdd and Ta values.
2. Typical values are at V
CC
= 1.8V, +25°C ambient and maximum loading.
3. This parameter is determined by device characterization but is not production tested.
1.8V AC Characteristics
(Over Operating Range: V
DD
= 1.8V ± 0.15V, T
A
= -40° to 85°C)
Parameters
F
IN
t
R
/t
F
t
PLH,
t
PHL(2)
t
SK(O)(3)
t
SK(P)(3)
t
SK(T)(3)
tdc_in
tdc_out
Input Frequency
CLKn Rise/Fall Time
Propagation Delay BUF_IN to CLKn
Output to Output Skew between any two
outputs of the same device @ same transition
Pulse Skew between opposite transitions
(t
PHL
-t
PLH
) of the same output
Part to Part Skew between two identical out-
puts of different parts on the same board
(4)
Duty Cycle In @ 1ns edge rate
Duty Cycle Out
C
L
= 5pF, 125 MHz
Outputs are measured
@ Vdd/2
40
40
20% to 80%
1.0
2.0
100
200
Description
Test Conditions
(1)
Min.
0
Typ
Max.
180
1.0
3.0
150
275
300
60
60
%
ps
Units
MHz
ns
ns
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew measured at worse cast temperature (max. temp).
4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
06-0035
3
PS8822B
04/03/06
PI6C10804
1.8V/2.5V, 250MHz, 1:4 Networking Clock Buffer
Power Supply Characteristics
Parameters
I
DDQ
I
DD_TOT
∆I
CC
Description
Quiescent Power
Supply Current
Total Power Supply
Current
V
DD
= 2.7V
V
DD
= 1.95V
V
DD
= 2.7V
V
DD
= 1.95V
Test Conditions
(1)
V
IN
= GND or V
DD
All Outputs Toggling,
C
L
= 5pF, F
IN
= 125MHz
V
INx
= Vdd - 0.6V
(3)
V
INx
= Vdd - 0.6V
(3)
Min.
Typ.
(2)
Max.
10
10
20
15
200
200
Units
µA
mA
µA
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics.
2. Typical values are at V
CC
= 1.8V or 2.5V, and +25°C ambient.
3. Per TTL driven input (V
IN
=
V
DD
- 0.6V);
all other inputs at V
CC
or GND.
Static Supply Current V
DD
= 2.7V
per inputs @ High
V
DD
= 1.95V
Level
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(1)
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
2.0
1.7
Max.
4
6
Units
pF
C
IN
Note:
1.
C
OUT
This parameter is determined by device characterization but is not production tested.
Test Circuits for All Outputs
½
½½
½½½½½
½½½½½½½½½½
½½½½½½½½½½
½½½
½½½½½½
½½½½½½
½
½½
½½½
Definitions:
C
L
= Load capacitance: includes jig and probe capacitance.
06-0035
4
PS8822B
04/03/06
PI6C10804
1.8V/2.5V, 250MHz, 1:4 Networking Clock Buffer
Switching Waveforms
Propagation Delay
½
½½
½½½½½
½
½½½
½½½½½½
½
½
½
½
Pulse Skew – t
SK(P)
½½½
½½½½½
½
½½½
½½½½½
½
½½½
½½½½½
½
½½
½
½½
½½½½½
½
½½
½
½½½
½½
½
½½
½½½½½
½
½½
½½½½½½
½
½½½½½
½½½½½½
½½½½½½
½
½½½½
½
Output Skew – t
SK(O)
Vdd
Input
t
PLHx
CLKx
t
SK(O)
CLKy
t
PLHy
t
SK(O)
= | t
PLHy -
t
PLHx
|
or
Package Skew – t
SK(T)
Vdd
Input
t
PLH1
Part #1
Output
t
SK(T)
Part #2
Output
t
PLH2
t
SK(T)
= | t
PLH2 -
t
PLH1
|
or
Vdd/2
t
PHLx
Vdd/2
t
PHL1
0V
V
OH
Vdd/2
V
OL
t
SK(O)
V
OH
Vdd/2
t
PHLy
0V
V
OH
Vdd/2
t
SK(T)
V
OL
V
OH
Vdd/2
V
OL
V
OL
t
PHL2
| t
PHL2 -
t
PHL1
|
| t
PHLy -
t
PHLx
|
06-0035
5
PS8822B
04/03/06
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