MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
8
1
SCALE 2:1
D
A
B
DFN8
CASE 506AL−01
ISSUE A
DATE 20 DEC 2005
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30mm.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
MILLIMETERS
MIN
NOM MAX
0.80
0.90
1.00
0.00
0.03
0.05
0.20 REF
0.35
0.40
0.45
3.30 BSC
0.95
1.05
1.15
3.30 BSC
1.80
1.90
2.00
0.80 BSC
0.21
−−−
−−−
0.30
0.40
0.50
PIN ONE
REFERENCE
2X
0.15 C
2X
0.15 C
0.10 C
8X
0.08 C
D2
8X
L
8X
K
STYLE 1:
PIN 1. IN
2. GND
3. CNTRL
4. DRAIN
5. SOURCE
6. GATE
7. OUT
8. VCC
1
2.95
2X
1.20
1.95
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
STATUS: ON SEMICONDUCTOR STANDARD
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
©
Semiconductor Components Industries, LLC, 2002
Case Outline Number:
http://onsemi.com
DESCRIPTION: DFN8, 3.3X3.3 MM, 0.8 MM PITCH, DUAL FLAG
October, 2002 − Rev. 0
PAGE 1 OF
XXX
2
1
DOCUMENT NUMBER:
98AON20636D
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1
8
E
TOP VIEW
(A3)
A
GENERIC
MARKING DIAGRAM*
SIDE VIEW
A1
D2
4
e
XXXX
A
Y
WW
E2
= Specific Device Code
= Assembly Location
= Year
= Work Week
C
SEATING
PLANE
1
XXXX
AYWW
2X
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “
G”,
may or may not be present.
b
0.10 C A B
0.05 C
NOTE 3
5
8X
SOLDERING FOOTPRINT*
3.60
8X
BOTTOM VIEW
0.55
0.45
0.80
PITCH
2X
0.60
DOCUMENT NUMBER:
98AON20636D
PAGE 2 OF 2
ISSUE
O
A
REVISION
RELEASE FOR PRODUCTION. REQ. BY S. CHANG.
ADDED SOLDER FOOTPRINT. REQ. BY S. CHANG.
DATE
08 APR 2005
20 DEC 2005
ON Semiconductor
and
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©
Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 01A
Case Outline Number:
506AL
FPGA/CPLD
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