Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state
74ALVC244
FEATURES
•
Wide supply voltage range from 1.65 to 3.6 V
•
3.6 V tolerant inputs/outputs
•
CMOS low power consumption
•
Direct interface with TTL levels (2.7 to 3.6 V)
•
Power-down mode
•
Latch-up performance exceeds 250 mA
•
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V)
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay nAn to nYn
DESCRIPTION
The 74ALVC244 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC244 is an octal non-inverting buffer/line driver
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs 1OE and 2OE. A HIGH on nOE
causes the outputs to assume a high-impedance
OFF-state. Schmitt-trigger action at all inputs makes the
circuit highly tolerant for slower input rise and fall times.
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
TYPICAL
2.7
ns
ns
ns
ns
UNIT
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
2.0
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
2.3
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
2.2
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
input capacitance
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
3.5
20
pF
pF
2003 Sep 08
2
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state
74ALVC244
FUNCTION TABLE
See note 1.
INPUT
nOE
L
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74ALVC244D
74ALVC244PW
74ALVC244BQ
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
SYMBOL
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
GND
data input
bus output
data input
bus output
data input
bus output
data input
bus output
ground (0 V)
DESCRIPTION
output enable input (active LOW)
TEMPERATURE
RANGE
−40
to +85
°C
−40
to +85
°C
−40
to +85
°C
PINS
20
20
20
PACKAGE
SO20
TSSOP20
DHVQFN20
MATERIAL
plastic
plastic
plastic
CODE
SOT163-1
SOT360-1
SOT764-1
nAn
L
H
X
OUTPUT
nYn
L
H
Z
PIN
11
12
13
14
15
16
17
18
19
20
SYMBOL
2A3
1Y3
2A2
1Y2
2A1
1Y1
2A0
1Y0
2OE
V
CC
data input
DESCRIPTION
bus output
data input
bus output
data input
bus output
data input
bus output
output enable input (active LOW)
supply voltage
2003 Sep 08
3
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state
74ALVC244
handbook, halfpage
1OE
1
VCC
20
19
18
17
16
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
handbook, halfpage
1A0
1OE 1
1A0 2
2Y0 3
1A1 4
2Y1 5
1A2 6
2Y2 7
1A3 8
2Y3 9
GND 10
MNA162
2
3
4
5
20 VCC
19 2OE
18 1Y0
17 2A0
2Y1
16 1Y1
2Y0
1A1
244
GND
(1)
1A2
2Y2
1A3
6
7
8
9
10
Top view
GND
11
2A3
MNA981
15 2A1
14 1Y2
13 2A2
15
14
13
12
12 1Y3
11 2A3
2Y3
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1
EN
18
16
14
12
handbook, halfpage
2
17
4
15
6
13
8
11
1
19
1A0
2A0
1A1
2A1
1A2
2A2
1A3
2A3
1OE
2OE
1Y0
2Y0
1Y1
2Y1
1Y2
2Y2
1Y3
2Y3
18
3
16
5
14
7
12
9
2
4
6
8
19
EN
9
7
5
3
MNA169
11
13
MNA168
15
17
Fig.3 Logic symbol.
Fig.4 IEE/IEC logic symbol.
2003 Sep 08
4
PCB Design
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