LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems
unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.
1)
Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided
in the labeling, can be reasonably expected to result in a significant injury to the user.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
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2)
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PI7C21P100B
2-PORT PCI-X TO PCI-X BRIDGE
TABLE OF CONTENTS
1
2
3
DESCRIPTION................................................................................................................................... 9
FEATURES ......................................................................................................................................... 9
SIGNAL DEFINITIONS.................................................................................................................. 10
3.1
SIGNAL TYPES ....................................................................................................................... 10
3.2
SIGNALS .................................................................................................................................. 10
3.2.1
PRIMARY BUS INTERFACE SIGNALS............................................................................... 10
3.2.2
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION.......................................... 12
3.2.3
SECONDARY BUS INTERFACE SIGNALS......................................................................... 13
3.2.4
SECONDARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION.................................... 14
3.2.5
CLOCK SIGNALS................................................................................................................. 15
3.2.6
STRAPPING PINS AND MISCELLANEOUS SIGNALS ...................................................... 16
3.2.7
JTAG BOUNDARY SCAN AND TEST SIGNALS ................................................................. 17
3.2.8
TEST SIGNALS..................................................................................................................... 18
3.2.9
POWER AND GROUND SIGNALS...................................................................................... 18
3.3
PIN LIST ................................................................................................................................... 19
4
PCI BUS OPERATION.................................................................................................................... 22
4.1
TYPES OF TRANSACTIONS ................................................................................................. 22
4.2
WRITE TRANSACTIONS ....................................................................................................... 23
4.2.1
MEMORY WRITE TRANSACTIONS .................................................................................... 23
4.2.1.1
PCI-X TO PCI-X
.................................................................................................................... 24
4.2.1.2
PCI TO PCI
.............................................................................................................................. 24
4.2.1.3
PCI TO PCI-X
......................................................................................................................... 24
4.2.1.4
PCI-X TO PCI
......................................................................................................................... 25
4.2.2
DELAYED/SPLIT WRITE TRANSACTIONS........................................................................ 25
4.2.3
IMMEDIATE WRITE TRANSACTIONS ............................................................................... 25
4.3
READ TRANSACTIONS......................................................................................................... 25
4.3.1
MEMORY READ TRANSACTIONS...................................................................................... 26
4.3.1.1
PCI-X TO PCI-X
.................................................................................................................... 26
4.3.1.2
PCI TO PCI
.............................................................................................................................. 26
4.3.1.3
PCI TO PCI-X
......................................................................................................................... 26
4.3.1.4
PCI-X TO PCI
......................................................................................................................... 27
4.3.2
I/O READ.............................................................................................................................. 27
4.3.3
CONFIGURATION READ ................................................................................................... 27
4.3.3.1
TYPE 1 CONFIGURATION READ
................................................................................... 27
4.3.3.2
TYPE 0 CONFIGURATION READ
................................................................................... 28
4.3.4
NON-PREFETCHABLE AND DWORD READS.................................................................. 28
4.3.5
PREFETCHABLE READS.................................................................................................... 28
4.3.5.1
PCI-X TO PCI-X AND PCI-X TO PCI
............................................................................. 28
4.3.5.2
PCI TO PCI
.............................................................................................................................. 29
4.3.5.3
PCI TO PCI-X
......................................................................................................................... 29
4.3.6
DYNAMIC PREFETCH (CONVENTIONAL PCI MODE ONLY) ........................................ 29
4.4
CONFIGURATION TRANSACTIONS ................................................................................... 29
4.4.1
TYPE 0 ACCESS TO PI7C21P100B .................................................................................... 30
4.4.2
TYPE 1 TO TYPE 0 CONVERSION ..................................................................................... 30
4.4.3
TYPE 1 TO TYPE 1 FORWARDING.................................................................................... 32
4.4.4
SPECIAL CYCLES ............................................................................................................... 32
5
TRANSACTION ORDERING ........................................................................................................ 33
5.1
GENERAL ORDERING GUIDELINES .................................................................................. 33
Page 5 of 79
November 2005 – Revision 1.02
ARM Technology
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