a6850
®
Asynchronous Communications
Interface Adapter
Data Sheet
September 1996, ver. 1
Features
s
s
s
s
s
s
s
a6850
MegaCore function implementing an asychronous
communications interface adapter (ACIA)
Optimized for FLEX
®
and MAX
®
architectures
Programmable word lengths, stop bits, and parity
Offers divide-by-1, -16, or -64 mode
Includes error detection
Uses approximately 237 FLEX logic elements (LEs)
Functionally based on the Motorola MC6850 device, except as noted
in the
“Variations & Clarifications” section on page 94
General
Description
The
a6850
MegaCore function implements an ACIA, which is a universal
asynchronous receiver/transmitter (UART). The
a6850
provides an
interface between a microprocessor and a serial communications channel.
The
a6850
receives and transmits data in a variety of configurations,
including 7- or 8-bit data words, with odd, even, or no parity, and 1 or 2
stop bits. See
Figure 1.
Figure 1. a6850 Symbol
A6850
nCTS
nDCD
E
nRESET
RS
RnW
RXCLK
RXDATA
TXCLK
CS[2..0]
DI[7..0]
nIRQ
nRTS
TXDATA
DO[7..0]
Altera Corporation
A-DS-A6850-01
81
a6850 Asynchronous Communications Interface Adapter Data Sheet
Table 1
describes the input and output ports of the
a6850.
Table 1. a6850 Ports
Name
ncts
ndcd
Type
Input
Input
Polarity
Low
Low
Description
Clear to send, a modem signal name. The
ncts
input inhibits the
assertion of the transmit data register empty (tdre) status bit.
Data carrier detect, a modem signal name. When the
ndcd
signal
transitions from low to high, an interrupt to the microprocessor is
generated.
Enable for the microprocessor interface. When
e
is high, the
microprocessor can access the registers.
Asynchronous reset for the registers and control logic. The
nreset
pin was not included in the original MC6850 device.
Register select. This input selects the register based on
rnw.
If
rnw
is high (signaling a read operation), then
rs
= 1 selects the receiver
data register and
rs
= 0 selects the status register. However, if
rnw
is low (signaling a write operation), then
rs
= 1 selects the
transmitter data register and
rs
= 0 selects the control register.
Read/write register controls. When
rnw
is high, the microprocessor
reads the registers; when
rnw
is low, the microprocessor writes to
the registers.
Receive clock. The receive control register samples
rxdata
based
on
rxclk
and the state of the counter divide select (cds) bits in the
control register.
Receive data. Serial data input from the modem or peripheral.
Transmit clock. Data is asserted to
txdata
on the falling edge of
txclk.
Chip select from the microprocessor. Chip select must be in the
110
state for the
a6850
to be selected.
Parallel data input from the microprocessor or other controlling
device.
Interrupt request to microprocessor.
Request to send. Bits 5 and 6 (transmitter control bits) of the control
register set the
nrts
bit. The
nrts
signal is asserted when bit 6 is
low, or bits 5 and 6 are both high.
Transmit data. Serial output to the modem or peripheral.
Parallel data output to the microprocessor or other controlling device.
e
nreset
rs
Input
Input
Input
High
Low
–
rnw
Input
Low
rxclk
Input
–
rxdata
txclk
cs[2..0]
di[7..0]
nirq
nrts
Input
Input
Input
Input
Output
Output
–
–
–
–
Low
Low
txdata
do[7..0]
Output
Output
–
–
82
Altera Corporation
a6850 Asynchronous Communications Interface Adapter Data Sheet
Functional
Description
Figure 2
shows the
a6850
block diagram.
Figure 2. a6850 Block Diagram
Transmitter
Output
Shift
Register/
Parity
Generate
di
8
Transmitter
Data
Register
8
txclk
txdata
8
Control
Register
e
rnw
cs
rs
3
Transmitter
Control
ncts
ndcd
Bus
Interface
Contro
l
Receiver
nrts
nirq
8
8
8
Status
Register
Receiver
Control
do
Receiver
Data
Register
8
Input
Shift
Register/
Parity
Check
rxdata
rxclk
Registers
The
a6850
contains the following registers:
s
s
s
s
Transmitter data register
Receiver data register
Control register
Status register
Altera Corporation
83
a6850 Asynchronous Communications Interface Adapter Data Sheet
Transmitter Data Register
The transmitter data register (TDR) is written to by the microprocessor or
other controlling device. Once the existing data bits in the output shift
register are completely transmitted out, the TDR transfers new data into
the output shift register.
Receiver Data Register
The receiver data register (RDR) is written to by the input shift register.
Once the existing data in the RDR is read, the input shift register transfers
new data into the RDR. If 7-bit data is selected, bit 7 is set to a logic low.
Control Register
The control register contains the control bits shown in
Table 2.
Table 2. Control Register Bits
Data Bit
0
1
2
3
4
5
6
7
Signal Name
Counter divide select 0 (cds0)
Counter divide select 1 (cds1)
Word select 0 (ws0)
Word select 1 (ws1)
Word select 2 (ws2)
Transmitter control 0 (tc0)
Transmitter control 1 (tc1)
Receive interrupt enable (rie)
Counter Divide Select
Bits 0 and 1 of the control register are the
cds
bits, which determine the
ratio between the data rate and the clocks. The ratios when transmitting
and receiving are identical. The
cds
bits can also be used to reset the
a6850
to a known state. See
Table 3.
84
Altera Corporation
a6850 Asynchronous Communications Interface Adapter Data Sheet
Table 3. Counter Divide Select Bits
cds1
0
cds0
0
Function
Divide-by-1 mode. Clock and data rate are identical. External
logic is responsible for synchronizing
rxdata
to
rxclk.
The
rxdata
signal is sampled on the rising edge of
rxclk,
and
the
txdata
signal is asserted on the falling edge of
txclk.
Divide-by-16 mode. The clock rate is 16 times the data rate.
After start bit detection (rxdata low), the
rxdata
signal is
sampled on the 9th rising edge of
rxclk.
After writing to the
transmitter data register, the
txdata
signal is asserted on
the first falling edge of
txclk
and every 16 clocks thereafter.
Divide-by-64 mode. The clock rate is 64 times the data rate.
After start bit detection (rxdata low), the
rxdata
signal is
sampled on the 33rd rising edge of
rxclk.
After writing to the
transmitter data register, the
txdata
signal is asserted on
the first falling edge of
txclk
and every 64 clocks thereafter.
Master reset. When master reset is selected, the
a6850
is
reset to a known state; the status register is cleared, and the
transmit and receive operations are halted and initialized.
0
1
1
0
1
1
Word Select
Bits 2, 3, and 4 of the control register are the
ws
bits, which determine the
word length, parity, and number of stop bits. See
Table 4.
Table 4. Word Select Bits
ws2
0
0
0
0
1
1
1
1
ws1
0
0
1
1
0
0
1
1
ws0
0
1
0
1
0
1
0
1
Word
Length
7
7
7
7
8
8
8
8
Stop Bits
2
2
1
1
2
1
1
1
Parity
Even
Odd
Even
Odd
None
None
Even
Odd
Altera Corporation
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