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SY88843VKITR

Description
3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD
File Size121KB,11 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
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SY88843VKITR Overview

3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD

Micrel, Inc.
3.3V/5V 3.2Gbps CML LOW-POWER
LIMITING POST AMPLIFIER w/TTL SD
SY88843V
SY88843V
FEATURES
s
Multi-rate up to 3.2Gbps operation
s
Wide gain-bandwidth product
38dB differential gain
2GHz 3dB bandwidth
s
Low noise 50
CML data outputs
800mV
PP
output swing
60ps edge rates
5ps
RMS
typ. random jitter
15ps
PP
typ. deterministic jitter
s
Chatter-free, Signal-Detect (SD) output
4.6dB electrical hysteresis
OC-TTL output with internal 4.75k
pull-up
resistor
s
Programmable SD sensitivity using single external
resistor
s
Internal 50
data input termination
s
TTL EN input allows feedback from SD
s
Wide operating range
Single 3.3V
±
10% or 5V
±
10% power supply
–40
°
C to +85
°
C industrial temperature range
s
Available in tiny 10-pin EPAD-MSOP and
16-pin MLF™ packages
DESCRIPTION
The SY88843V low-power limiting post amplifier is
designed for use in fiber-optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88843V
quantizes these signals and outputs typically 800mV
PP
voltage-limited waveforms.
The SY88843V operates from a single +3.3V
±10%
or
+5V
±10%
power supply, over an industrial temperature
range of –40°C to +85°C. With its wide bandwidth and high
gain, signals with data rates up to 3.2Gbps and as small as
10mVp-p can be amplified to drive devices with CML inputs
or AC-coupled PECL inputs.
The SY88843V incorporates a signal detect (SD), open-
collector TTL output with internal 4.75kΩ pull-up resistor. A
programmable, loss-of-signal level set pin (SDLVL) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SDLVL
and de-asserts low otherwise. SD can be fed back to the
enable (EN) input to maintain output stability under a loss
of signal condition. EN asserts the true output signal without
removing the input signal. Typically 4.6dB SD hysteresis is
provided to prevent chattering.
Please see Micrel’s website at www.micrel.com for a
complete selection of optical module ICs. The following table
summarizes the differences between devices in Micrel’s
latest family of Limiting Amplifiers.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
Integrated 50
Part Number Input Termination
SY88773V
No
No
Yes
Yes
SY88823V
SY88843V
SY88973V
LOS
or SD
LOS
SD
SD
LOS
Active LOW
or HIGH Enable
LOW
HIGH
HIGH
LOW
APPLICATIONS
s
1.25Gbps and 2.5Gbps Gigabit Ethernet
s
1.062Gbps and 2.125Gbps Fibre Channel
s
155Mbps, 622Mbps, 1.25Gbps, and 2.5Gbps SONET/
SDH
s
Gigabit interface converter (GBIC)
s
Small form factor (SFF) and small form factor
pluggable (SFP) transceivers
s
Parallel 10G Ethernet
s
High-gain line driver and line receiver
Table 1. Limiting Amplifiers Selection Guide
TYPICAL PERFORMANCE
3.3V, 25°C, 10mV
pp
Input
@3.2Gbps 2
31
–1 PRBS, R
LOAD
= 50Ω to V
CC
Output Swing
(75mV/div.)
Micro
LeadFrame and MLF are trademarks of Amkor Technology
M9999-110905
hbwhelp@micrel.com or (408) 955-1690
TIME (50ps/div.)
Rev.: C
Amendment: /0
1
Issue Date: November 2005

SY88843VKITR Related Products

SY88843VKITR SY88843VKI SY88843VMI SY88843VMITR SY88843VMGTR SY88843VEYTR
Description 3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD 3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD 3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD 3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD 3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD 3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD
Is it Rohs certified? - - incompatible incompatible conform to conform to
Parts packaging code - - DFN DFN DFN MSOP
package instruction - - HVQCCN, LCC16,.12SQ,20 HVQCCN, LCC16,.12SQ,20 HVQCCN, HTSSOP,
Contacts - - 16 16 16 10
Reach Compliance Code - - _compli _compli compli compli
JESD-30 code - - S-XQCC-N16 S-XQCC-N16 S-XQCC-N16 S-PDSO-G10
JESD-609 code - - e0 e0 e4 e3
length - - 3 mm 3 mm 3 mm 3 mm
Humidity sensitivity level - - 2 2 2 3
Number of functions - - 1 1 1 1
Number of terminals - - 16 16 16 10
Maximum operating temperature - - 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature - - -40 °C -40 °C -40 °C -40 °C
Package body material - - UNSPECIFIED UNSPECIFIED UNSPECIFIED PLASTIC/EPOXY
encapsulated code - - HVQCCN HVQCCN HVQCCN HTSSOP
Package shape - - SQUARE SQUARE SQUARE SQUARE
Package form - - CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) - - 240 240 260 260
Certification status - - Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height - - 0.95 mm 0.95 mm 0.95 mm 1.1 mm
Nominal supply voltage - - 3.3 V 3.3 V 3.3 V 3.3 V
surface mount - - YES YES YES YES
Telecom integrated circuit types - - ATM/SONET/SDH SUPPORT CIRCUIT ATM/SONET/SDH SUPPORT CIRCUIT ATM/SONET/SDH SUPPORT CIRCUIT ATM/SONET/SDH SUPPORT CIRCUIT
Temperature level - - INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface - - Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Nickel/Palladium/Gold (Ni/Pd/Au) Matte Tin (Sn)
Terminal form - - NO LEAD NO LEAD NO LEAD GULL WING
Terminal pitch - - 0.5 mm 0.5 mm 0.5 mm 0.5 mm
Terminal location - - QUAD QUAD QUAD DUAL
Maximum time at peak reflow temperature - - 30 30 40 40
width - - 3 mm 3 mm 3 mm 3 mm

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