VRS51x550/560
Datasheet
Rev 1.3
Versa 8051 MCUs with 8/16KB Flash
Overview
The VRS51x550 and VRS51x560 are low-cost 8-bit
microcontrollers based on the standard 80C51
microcontroller architecture. They are pin compatible
drop-in replacements for the 8051
Ideal for a wide range of applications requiring low to
midrange amounts of program/data memory, coupled
with streamlined peripheral support, the VRS51x550/560
devices feature 8KB/16KB, of Flash memory
(respectively), 256 bytes of RAM, a UART, three 16-bit
timers, a watchdog timer and power saving modes.
The VRS51x550 is available in 3.3 (VRS51L550) or 5
volt versions (VRS51C550), while the VRS51x560 is
available in a 5 volt version (VRS51C560). All devices
come in PLCC-44, QFP-44 and DIP-40 packages and
operate in the industrial temperature range. Flash can
be programmed using a parallel programmer available
from Ramtron or with a third party commercial
programmer.
F
IGURE
1: VRS51
X
550 / VRS51
X
560 F
UNCTIONAL
D
IAGRAM
P1.4
P1.3
Feature Set
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
80C51/80C52 pin compatible
12 clock periods per machine cycle
8KB / 16KB on-chip Flash memory
256 Bytes on-chip data RAM
32 I/O lines on four 8-bit ports
Full duplex serial port (UART)
3, 16-bit Timers/Counters
Watchdog Timer
8-bit Unsigned Division / Multiply
BCD arithmetic
Direct and Indirect Addressing
Two levels of interrupt priority and nested interrupts
Power saving modes
Code protection function
Operates at a clock frequency of up to 40MHz
Low EMI (inhibit ALE)
Programming voltage: 12V
Industrial Temperature range (-40°C to +85°C)
5V and 3V versions available
(see ordering information)
F
IGURE
2: VRS51
X
550 / VRS51
X
560 PLCC
AND
QFP P
INOUT
D
IAGRAMS
P1.2
T2EX/P1.1
P0.0/AD0
P0.2/AD2
P1.5
P1.6
7
6
P0.1/AD1
T2/P1.0
VDD
NC
1
P0.3/AD3
40
39
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA
NC
ALE
#PSEN
P2.7/A15
8051
PROCESSOR
ADDRESS/
DATA BUS
P1.7
RESET
RXD/P3.0
NC
TXD/P3.1
#INT0/P3.2
VRS51x550/560
PLCC-44
8KB / 16KB
FLASH
256
Bytes of RAM
PORT 0
8
#INT1/P3.3
T0/P3.4
T1/P3.5
17
18
29
28
P2.6/A14
P2.5/A13
#RD/P3.7
P2.0/A8
P2.1/A9
P2.2/A10
XTAL2
XTAL1
#WR/P3.6
UART
PORT 2
8
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#PSEN
P2.7/A15
P2.6/A14
P2.5/A13
23
22
#EA
2 INTERRUPT
INPUTS
TIMER 0
TIMER 1
TIMER 2
RESET
POWER
CONTROL
WATCHDOG
TIMER
PORT 3
8
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
NC
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
44
34
33
ALE
NC
P2.4/A12
P2.3/A11
VSS
NC
PORT 1
8
P2.4/A12
P2.3/A11
P2.2/A10
VRS51x550/560
QFP-44
P2.1/A9
P2.0/A8
NC
VSS
XTAL1
XTAL2
12
11
#RD/P3.7
#WR/P3.6
1
P1.5
P1.6
P1.7
RESET
RXD/P3.0
NC
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
Ramtron International Corporation
1850 Ramtron Drive Colorado Springs
Colorado, USA, 80921
?
?
?
http://www.ramtron.com
MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208
1-800-545-FRAM, 1-719-481-7000
T0/P3.4
T1/P3.5
page 1 of 40
VRS51x550/560
Pin Descriptions for QFP-44
T
ABLE
1: P
IN
D
ESCRIPTIONS FOR
QFP-44/
QFP
- 44
Name
I/O
Function
QFP
- 44
Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
P1.5
P1.6
P1.7
RES
RXD
P3.0
NC
TXD
P3.1
#INT0
P3.2
#INT1
P3.3
T0
P3.4
T1
P3.5
#WR
P3.6
#RD
P3.7
XTAL2
XTAL1
VSS
NC
P2.0
A8
P2.1
A9
P2.2
A10
P2.3
A11
P2.4
A12
P2.5
A13
I/O
I/O
I/O
I
I
I/O
-
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
O
I/O
O
I/O
O
I
-
-
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
Bit 5 of Port 1
Bit 6 of Port 1
Bit 7 of Port 1
Reset
Receive Data
Bit 0 of Port 3
No Connect
Transmit Data &
Bit 1 of Port 3
External Interrupt 0
Bit 2 of Port 3
External Interrupt 1
Bit 3 of Port 3
Timer 0
Bit 4 of Port 3
Timer 1 & 3
Bit 5 of Port
Ext. Memory Write
Bit 6 of Port 3
Ext. Memory Read
Bit 7 of Port 3
Oscillator/Crystal Output
Oscillator/Crystal In
Ground
No Connect
Bit 0 of Port 2
Bit 8 of External Memory Address
Bit 1 of Port 2
Bit 9 of External Memory Address
Bit 2 of Port 2
Bit 10 of External Memory Address
Bit 3 of Port 2 &
Bit 11 of External Memory Address
Bit 4 of Port 2
Bit 12 of External Memory Address
Bit 5 of Port 2
Bit 13 of External Memory Address
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P2.6
A14
P2.7
A15
#PSEN
ALE
NC
#EA
P0.7
AD7
P0.6
AD6
P0.5
AD5
P0.4
AD4
P0.3
AD3
P0.2
AD2
P0. 1
AD1
P0.0
AD0
VDD
NC
T2
P1.0
T2EX
P1.1
P1.2
P1.3
P1.4
I/O
O
I/O
O
O
O
-
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I
I/O
I
I/O
I/O
I/O
I/O
Bit 6 of Port 2
Bit 14 of External Memory Address
Bit 7 of Port 2
Bit 15 of External Memory Address
Program Store Enable
Address Latch Enable
No Connect
External Access
Bit 7 Of Port 0
Data/Address Bit 7 of External Memory
Bit 6 of Port 0
Data/Address Bit 6 of External Memory
Bit 5 of Port 0
Data/Address Bit 5 of External Memory
Bit 4 of Port 0
Data/Address Bit 4 of External Memory
Bit 3 Of Port 0
Data/Address Bit 3 of External Memory
Bit 2 of Port 0
Data/Address Bit 2 of External Memory
Bit 1 of Port 0 & Data
Address Bit 1 of External Memory
Bit 0 Of Port 0 & Data
Address Bit 0 of External Memory
VCC
No Connect
Timer 2 Clock Out
Bit 0 of Port 1
Timer 2 Control
Bit 1 of Port 1
Bit 2 of Port 1
Bit 3 of Port 1
Bit 4 of Port 1
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA
P2.7/A15
P2.6/A14
33 32 31 30 29 28 27 26 25 24 23
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
NC
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
P2.5/A13
#PSEN
NC
ALE
22
21
20
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
NC
VSS
XTAL1
XTAL2
#RD/P3.7
#WR/P3.6
VRS51x550/560
QFP-44
19
18
17
16
15
14
13
12
9 10 11
P1.5
P1.6
P1.7
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
________________________________________________________________________________________________
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page 2 of 40
RXD/P3.0
T0/P3.4
T1/P3.5
RESET
NC
VRS51x550/560
Pin Descriptions for PLCC-44
T
ABLE
2: P
IN
D
ESCRIPTIONS FOR
PLCC-44
PLCC
- 44
Name
I/O
Function
PLCC
- 44
Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NC
T2
P1.0
T2EX
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RES
RXD
P3.0
NC
TXD
P3.1
#INT0
P3.2
#INT1
P3.3
T0
P3.4
T1
P3.5
#WR
P3.6
#RD
P3.7
XTAL2
XTAL1
VSS
NC
-
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
-
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
O
I/O
O
I/O
O
I
-
-
No Connect
Timer 2 Clock Out
Bit 0 of Port 1
Timer 2 Control
Bit 1 of Port 1
Bit 2 of Port 1
Bit 3 of Port 1
Bit 4 of Port 1
Bit 5 of Port 1
Bit 6 of Port 1
Bit 7 of Port 1
Reset
Receive Data
Bit 0 of Port 3
No Connect
Transmit Data &
Bit 1 of Port 3
External Interrupt 0
Bit 2 of Port 3
External Interrupt 1
Bit 3 of Port 3
Timer 0
Bit 4 of Port 3
Timer 1 & 3
Bit 5 of Port
Ext. Memory Write
Bit 6 of Port 3
Ext. Memory Read
Bit 7 of Port 3
Oscillator/Crystal Output
Oscillator/Crystal In
Ground
No Connect
24
25
26
27
28
29
30
31
32
33
34
35
36
P2.0
A8
P2.1
A9
P2.2
A10
P2.3
A11
P2.4
A12
P2.5
A13
P2.6
A14
P2.7
A15
#PSEN
ALE
NC
#EA
P0.7
AD7
P0.6
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
O
O
-
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
37
AD6
P0.5
38
AD5
P0.4
39
AD4
P0.3
40
AD3
P0.2
41
P1.2
T2EX/P1.1
AD2
P0. 1
AD1
P0.0
AD0
VDD
P1.4
P1.3
VDD
42
43
P1.5
P1.6
P1.7
RESET
RXD/P3.0
NC
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
7
8
9
10
11
12
13
14
15
16
6
5
4
3
2
44 43 42 41 40
1
39
38
37
36
35
34
33
32
31
30
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA
NC
ALE
#PSEN
P2.7/A15
P2.6/A14
P2.5/A13
44
Bit 0 of Port 2
Bit 8 of External Memory Address
Bit 1 of Port 2
Bit 9 of External Memory Address
Bit 2 of Port 2
Bit 10 of External Memory Address
Bit 3 of Port 2 &
Bit 11 of External Memory Address
Bit 4 of Port 2
Bit 12 of External Memory Address
Bit 5 of Port 2
Bit 13 of External Memory Address
Bit 6 of Port 2
Bit 14 of External Memory Address
Bit 7 of Port 2
Bit 15 of External Memory Address
Program Store Enable
Address Latch Enable
No Connect
External Access
Bit 7 Of Port 0
Data/Address Bit 7 of External
Memory
Bit 6 of Port 0
Data/Address Bit 6 of External
Memory
Bit 5 of Port 0
Data/Address Bit 5 of External
Memory
Bit 4 of Port 0
Data/Address Bit 4 of External
Memory
Bit 3 Of Port 0
Data/Address Bit 3 of External
Memory
Bit 2 of Port 0
Data/Address Bit 2 of External
Memory
Bit 1 of Port 0 & Data
Address Bit 1 of External Memory
Bit 0 Of Port 0 & Data
Address Bit 0 of External Memory
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
VRS51x550/560
PLCC-44
17
18 19 20
P0.3/AD3
29
T2/P1.0
21 22 23 24 25 26 27 28
#RD/P3.7
NC
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
XTAL2
XTAL1
#WR/P3.6
________________________________________________________________________________________________
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page 3 of 40
P2.4/A12
VSS
NC
VRS51x550/560
Pin Descriptions for DIP-40
T
ABLE
3: P
IN
D
ESCRIPTIONS FOR
DIP-40
DIP40
Name
I/O
Function
DIP40
Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
T2
P1.0
T2EX
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RESET
RXD
P3.0
TXD
P3.1
#INT0
P3.2
#INT1
P3.3
T0
P3.4
T1
P3.5
#WR
P3.6
#RD
P3.7
XTAL2
XTAL1
VSS
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
O
I/O
O
I/O
O
I
-
Timer 2 Clock Out
Bit 0 of Port 1
Timer 2 Control
Bit 1 of Port 1
Bit 2 of Port 1
Bit 3 of Port 1
Bit 4 of Port 1
Bit 5 of Port 1
Bit 6 of Port 1
Bit 7 of Port 1
Reset
Receive Data
Bit 0 of Port 3
Transmit Data &
Bit 1 of Port 3
External Interrupt 0
Bit 2 of Port 3
External Interrupt 1
Bit 3 of Port 3
Timer 0
Bit 4 of Port 3
Timer 1 & 3
Bit 5 of Port
Ext. Memory Write
Bit 6 of Port 3
Ext. Memory Read
Bit 7 of Port 3
Oscillator/Crystal Output
Oscillator/Crystal In
Ground
21
22
23
24
25
26
27
28
29
30
31
32
P2.0
A8
P2.1
A9
P2.2
A10
P2.3
A11
P2.4
A12
P2.5
A13
P2.6
A14
P2.7
A15
#PSEN
ALE
#EA /
VPP
P0.7
AD7
P0.6
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
33
AD6
P0.5
34
AD5
P0.4
35
AD4
P0.3
36
T2 / P1.0
T2EX / P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RESET
RXD / P3.0
TXD / P3.1
#INT0 / P3.2
#INT1 / P3.3
T0 / P3.4
T1 / P3.5
#WR / P3.6
#RD / P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
VDD
P0.0 / AD0
P0.1 / AD1
P0.2 / AD2
P0.3 / AD3
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
#EA / VPP
ALE
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
AD3
P0.2
37
38
39
40
AD2
P0. 1
AD1
P0.0
AD0
VDD
Bit 0 of Port 2
Bit 8 of External Memory Address
Bit 1 of Port 2
Bit 9 of External Memory Address
Bit 2 of Port 2
Bit 10 of External Memory Address
Bit 3 of Port 2 &
Bit 11 of External Memory Address
Bit 4 of Port 2
Bit 12 of External Memory Address
Bit 5 of Port 2
Bit 13 of External Memory Address
Bit 6 of Port 2
Bit 14 of External Memory Address
Bit 7 of Port 2
Bit 15 of External Memory Address
Program Store Enable
Address Latch Enable
External Access
Flash programming voltage input
Bit 7 Of Port 0
Data/Address Bit 7 of External
Memory
Bit 6 of Port 0
Data/Address Bit 6 of External
Memory
Bit 5 of Port 0
Data/Address Bit 5 of External
Memory
Bit 4 of Port 0
Data/Address Bit 4 of External
Memory
Bit 3 Of Port 0
Data/Address Bit 3 of External
Memory
Bit 2 of Port 0
Data/Address Bit 2 of External
Memory
Bit 1 of Port 0 & Data
Address Bit 1 of External Memory
Bit 0 Of Port 0 & Data
Address Bit 0 of External Memory
Supply input
VRS51x550
VRS51x560
DIP-40
32
31
30
29
28
27
26
25
24
23
22
21
________________________________________________________________________________________________
www.ramtron.com
page 4 of 40
VRS51x550/560
Instruction Set
Mnemonic
Description
Size
(bytes)
1
2
1
2
1
2
2
2
2
2
2
2
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
2
3
1
1
2
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
1
Instr. Cycles
The following tables describe the instruction set of the
VRS51x550/560. The instructions are function and binary
code compatible with industry standard 8051s.
T
ABLE
4: L
EGEND FOR
I
NSTRUCTION
S
ET
T
ABLE
Symbol
A
Rn
Direct
@Ri
rel
bit
#data
#data 16
addr 16
addr 11
Function
Accumulator
Register R0-R7
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
Direct bit address
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
T
ABLE
5: VRS51
X
550/VRS51
X
560 I
NSTRUCTION
S
ET
Mnemonic
Description
Size
(bytes)
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
Instr. Cycles
Arithmetic instructions
ADD A, Rn
Add register to A
ADD A, direct
Add direct byte to A
ADD A, @Ri
Add data memory to A
ADD A, #data
Add immediate to A
ADDC A, Rn
Add register to A with carry
ADDC A, direct
Add direct byte to A with carry
ADDC A, @Ri
Add data memory to A with carry
ADDC A, #data
Add immediate to A with carry
SUBB A, Rn
Subtract register from A with borrow
SUBB A, direct
Subtract direct byte from A with borrow
SUBB A, @Ri
Subtract data mem from A with borrow
SUBB A, #data
Subtract immediate from A with borrow
INC A
Increment A
INC Rn
Increment register
INC direct
Increment direct byte
INC @Ri
Increment data memory
DEC A
Decrement A
DEC Rn
Decrement register
DEC direct
Decrement direct byte
DEC @Ri
Decrement data memory
INC DPTR
Increment data pointer
MUL AB
Multiply A by B
DIV AB
Divide A by B
DA A
Decimal adjust A
Logical Instructions
ANL A, Rn
AND register to A
ANL A, direct
AND direct byte to A
ANL A, @Ri
AND data memory to A
ANL A, #data
AND immediate to A
ANL direct, A
AND A to direct byte
ANL direct, #data
AND immediate data to direct byte
ORL A, Rn
OR register to A
ORL A, direct
OR direct byte to A
ORL A, @Ri
OR data memory to A
ORL A, #data
OR immediate to A
ORL direct, A
OR A to direct byte
ORL direct, #data
OR immediate data to direct byte
XRL A, Rn
Exclusive-OR register to A
XRL A, direct
Exclusive-OR direct byte to A
XRL A, @Ri
Exclusive-OR data memory to A
XRL A, #data
Exclusive-OR immediate to A
XRL direct, A
Exclusive-OR A to direct byte
XRL direct, #data
Exclusive-OR immediate to direct byte
CLR A
Clear A
CPL A
Compliment A
SWAP A
Swap nibbles of A
RL A
Rotate A left
RLC A
Rotate A left through carry
RR A
Rotate A right
RRC A
Rotate A right through carry
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1
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Boolean Instruction
CLR C
Clear Carry bit
CLR bit
Clear bit
SETB C
Set Carry bit to 1
SETB bit
Set bit to 1
CPL C
Complement Carry bit
CPL bit
Complement bit
ANL C,bit
Logical AND between Carry and bit
ANL C,#bit
Logical AND between Carry and not bit
ORL C,bit
Logical ORL between Carry and bit
ORL C,#bit
Logical ORL between Carry and not bit
MOV C,bit
Copy bit value into Carry
MOV bit,C
Copy Carry value into Bit
Data Transfer Instructions
MOV A, Rn
Move register to A
MOV A, direct
Move direct byte to A
MOV A, @Ri
Move data memory to A
MOV A, #data
Move immediate to A
MOV Rn, A
Move A to register
MOV Rn, direct
Move direct byte to register
MOV Rn, #data
Move immediate to register
MOV direct, A
Move A to direct byte
MOV direct, Rn
Move register to direct byte
MOV direct, direct
Move direct byte to direct byte
MOV direct, @Ri
Move data memory to direct byte
MOV direct, #data
Move immediate to direct byte
MOV @Ri, A
Move A to data memory
MOV @Ri, direct
Move direct byte to data memory
MOV @Ri, #data
Move immediate to data memory
MOV DPTR, #data
Move immediate to data pointer
MOVC A, @A+DPTR
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1
Move code byte relative DPTR to A
MOVC A, @A+PC
Move code byte relative PC to A
MOVX A, @Ri
Move external data (A8) to A
MOVX A, @DPTR
Move external data (A16) to A
MOVX @Ri, A
Move A to external data (A8)
MOVX @DPTR, A
Move A to external data (A16)
PUSH direct
Push direct byte onto stack
POP direct
Pop direct byte from stack
XCH A, Rn
Exchange A and register
XCH A, direct
Exchange A and direct byte
XCH A, @Ri
Exchange A and data memory
XCHD A, @Ri
Exchange A and data memory nibble
Branching Instructions
ACALL addr 11
Absolute call to subroutine
LCALL addr 16
Long call to subroutine
RET
Return from subroutine
RETI
Return from interrupt
AJMP addr 11
Absolute jump unconditional
LJMP addr 16
Long jump unconditional
SJMP rel
Short jump (relative address)
JC rel
Jump on carry = 1
JNC rel
Jump on carry = 0
JB bit, rel
Jump on direct bit = 1
JNB bit, rel
Jump on direct bit = 0
JBC bit, rel
Jump on direct bit = 1 and clear
JMP @A+DPTR
Jump indirect relative DPTR
JZ rel
Jump on accumulator = 0
JNZ rel
Jump on accumulator 1= 0
CJNE A
, direct, rel
Compare A, direct JNE relative
CJNE A, #d, rel
Compare A, immediate JNE relative
CJNE Rn, #d, rel
Compare reg, immediate JNE relative
CJNE @Ri, #d, rel
Compare ind, immediate JNE relative
DJNZ Rn, rel
Decrement register, JNZ relative
DJNZ direct, rel
Decrement direct byte, JNZ relative
Miscellaneous Instruction
NOP
No operation
Rn:
Any of the register R0 to R7
@Ri:
Indirect addressing using Register R0 or R1
#data: immediate Data provided with Instruction
#data16: Immediate data included with instruction
bit:
address at the bit level
rel:
relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d:
Immediate Data supplied with instruction
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