AT45DQ161-SSHD-B datasheet, PDF

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AT45DQ161-SSHD-B: DescriptionNOR Flash 16M, 85MHz 2.5-3.6V Serial Flash; Categorystorage; File Size3MB，82 Pages; ManufacturerAdesto Technologies

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AT45DQ161-SSHD-B Overview

NOR Flash 16M, 85MHz 2.5-3.6V Serial Flash

AT45DQ161-SSHD-B Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Adesto Technologies
Product Category	NOR Flash
RoHS	Details
Mounting Style	SMD/SMT
Package / Case	SOIC-8
Memory Size	16 Mbit
Maximum Clock Frequency	85 MHz
Interface Type	SPI
Organization	2 M x 8
Timing Type	Synchronous
Data Bus Width	8 bit
Supply Voltage - Min	2.5 V
Supply Voltage - Max	3.6 V
Supply Current - Max	26 mA
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Packaging	Tube
Memory Type	NOR
Speed	85 MHz
Architecture	Chip Erase
Factory Pack Quantity	98
Unit Weight	0.019048 oz

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AT45DQ161

16-Mbit DataFlash, 2.3V Minimum

SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support

Features



Single 2.3V - 3.6V supply



Serial Peripheral Interface (SPI) compatible



Supports SPI modes 0 and 3

™



Supports RapidS operation



Supports Dual-input and Quad-input Buffer Write



Supports Dual-output and Quad-output Read



Very high operating frequencies



85MHz (for SPI)



85MHz (for Dual-I/O and Quad-I/O)



Clock-to-output time (t

) of 6ns maximum



User configurable page size



512 bytes per page



528 bytes per page (default)



Page size can be factory pre-configured for 512 bytes



Two fully independent SRAM data buffers (512/528 bytes)



Allows receiving data while reprogramming the main memory array



Flexible programming options



Byte/Page Program (1 to 512/528 bytes) directly into main memory



Buffer Write



Buffer to Main Memory Page Program



Flexible erase options



Page Erase (512/528 bytes), Block Erase (4KB)



Sector Erase (128KB), Chip Erase (16-Mbits)



Program and Erase Suspend/Resume



Advanced hardware and software data protection features



Individual sector protection



Individual sector lockdown to make any sector permanently read-only



128-byte, One-Time Programmable (OTP) Security Register



64 bytes factory programmed with a unique identifier



64 bytes user programmable



Hardware and software controlled reset options



JEDEC Standard Manufacturer and Device ID Read



Low-power dissipation



500nA Ultra-Deep Power-Down current (typical)



3µA Deep Power-Down current (typical)



25µA Standby current (typical)



11mA Active Read current (typical at 20MHz)



Endurance: 100,000 program/erase cycles per page minimum (50,000 cycles

for extended temperature option)



Data retention: 20 years



Complies with full industrial temperature range (extended temperature optional)



Green (Pb/Halide-free/RoHS compliant) packaging options



8-lead SOIC (0.150" wide and 0.208" wide)



8-pad Ultra-thin DFN (5 x 6 x 0.6mm)



9-ball Ultra-thin UBGA (6 x 6 x 0.6mm)

8790E–DFLASH–1/2017

Table 1-1.

Symbol

Pin Configurations (Continued)

Name and Function

Write Protect (I/O

When the WP pin is asserted, all sectors specified for protection by the

Sector Protection Register will be protected against program and erase operations regardless

of whether the Enable Sector Protection command has been issued or not. The WP pin

functions independently of the software controlled protection method. After the WP pin goes

low, the contents of the Sector Protection Register cannot be modified.

The WP pin must be driven at all times or pulled-high using an external pull-up resistor.

If a program or erase command is issued to the device while the WP pin is asserted, the device

will simply ignore the command and perform no operation. The device will return to the idle

state once the CS pin has been deasserted. The Enable Sector Protection command and the

Sector Lockdown command, however, will be recognized by the device when the WP pin is

asserted.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection

will not be used. However, it is recommended that the WP pin also be externally connected to

whenever possible.

With the Quad-output Read Array command, the WP pin becomes an output pin (I/O

) and,

when used with other pins, allows four bits (on I/O

3-0

) of data to be clocked out on every falling

edge of SCK. The QE bit in the Configuration Register must be set in order for the WP pin to

be used as an I/O data pin.

Asserted

State

Type

WP (I/O

)

Low

Input/

Output

Reset (I/O

A low state on the reset pin (RESET) will terminate the operation in progress and

reset the internal state machine to an idle state. The device will remain in the reset condition as

long as a low level is present on the RESET pin. Normal operation can resume once the

RESET pin is brought back to a high level.

RESET

(I/O

)

With the Quad-output Read Array command, the RESET pin becomes an output pin (I/O

) and,

when used with other pins, allows four bits (on I/O

3-0

) of data to be clocked out on every falling

edge of SCK. The QE bit in the Configuration Register must be set in order for the RESET pin

to be used as an I/O data pin.

The device incorporates an internal power-on reset circuit, so there are no restrictions on the

RESET pin during power-on sequences. If this pin and feature is not utilized, then it is

recommended that the RESET pin be driven high externally.

GND

Device Power Supply:

The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be attempted.

Ground:

The ground reference for the power supply. GND should be connected to the system

ground.

—

Power

Ground

Input/

Low

Output

AT45DQ161

8790E–DFLASH–1/2017

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