6-output 3.3V PCIe Zero-Delay
Buffer
Description
The 9DBL0641 / 9DBL0651 devices are 3.3V members of
IDT's Full-Featured PCIe family. The 9DBL06 supports PCIe
Gen1-4 Common Clocked (CC) and PCIe Separate
Reference Independent Spread (SRIS) systems. It offers a
choice of integrated output terminations providing direct
connection to 85Ω or 100Ω transmission lines. The
9DBL06P1 can be factory programmed with a user-defined
power up default SMBus configuration.
9DBL0641 / 9DBL0651
DATASHEET
Features/Benefits
•
Direct connection to 100 (xx41) or 85 (xx51)
•
•
•
transmission lines; saves 24 resistors compared to
standard PCIe devices
149mW typical power consumption (PLL mode@3.3V);
eliminates thermal concerns
VDDIO allows 30% power savings at optional 1.05V;
maximum power savings
SMBus-selectable features allows optimization to customer
requirements:
–
control input polarity
–
control input pull up/downs
– slew rate for each output
– differential output amplitude
– output impedance for each output
– 50, 100, 125MHz operating frequency
Customer defined SMBus power up default can be
programmed into P1 device; allows exact optimization to
customer requirements
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device operation
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
•
•
•
•
•
•
•
•
•
•
•
6 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0641 default Z
OUT
= 100
9DBL0651 default Z
OUT
= 85
9DBL06P1 factory programmable defaults
•
•
•
•
•
•
•
•
•
Key Specifications
PCIe Gen1-2-3-4 CC compliant in ZDB mode
PCIe Gen2 SRIS compliant in ZDB mode
Supports PCIe Gen2-3 SRIS in fan-out mode
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Block Diagram
Note:
Default resistors are internal on xx41/xx51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DBL0641 / 9DBL0651 FEBRUARY 8, 2017
1
©2017 Integrated Device Technology, Inc.
9DBL0641 / 9DBL0651 DATASHEET
Pin Configuration
^CKPWRGD_PD#
40 39 38 37 36 35 34 33 32 31
vSADR_tri
1
^vHIBW_BYPM_LOBW#
2
FB_DNC
3
FB_DNC#
4
VDDR3.3
5
CLK_IN
6
CLK_IN#
7
GNDDIG
8
SCLK_3.3
9
SDATA_3.3
10
11 12 13 14 15 16 17 18 19 20
DIF0#
VDDDIG3.3
vOE0#
VDD3.3
VDDIO
VDDIO
DIF1#
DIF0
DIF1
NC
30
NC
29
vOE3#
28
DIF3#
27
DIF3
9DBL0641/51/P1
epad is GND
VDD3.3
26
VDDIO
25
VDDA3.3
24
vOE2#
23
DIF2#
22
DIF2
21
vOE1#
VDDIO
40-VFQFPN, 5mm x 5mm 0.4mm pin pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+
Read/Write bit
x
x
x
Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to transition
from 2.1V to 3.135V in <300usec.
Power Management Table
DIFx
SMBus
OEx# Pin
OEx bit
True O/P
Comp. O/P
1
0
X
X
X
Low
1
Low
1
Running
0
X
Low
1
Low
1
1
Running
1
0
Running
Running
1
1
Running
1
1
Low
1
Low
1. The output state is set by B11[1:0] (Low/Low default)
2. If Bypass mode is selected, the PLL will be off, and outputs will be running.
CKPWRGD_PD#
CLK_IN
PLL
Off
On
2
On
2
On
2
Power Connections
Pin Number
VDD
5
11
16, 31
25
12,17,26,32,
39
VDDIO
GND
41
8
41
41
Description
Input
receiver
analog
Digital Power
DIF outputs,
Logic
PLL Analog
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
6-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
2
VDDIO
vOE5#
vOE4#
DIF5#
DIF4#
DIF5
DIF4
FEBRUARY 8, 2017
9DBL0641 / 9DBL0651 DATASHEET
Pin Descriptions
PIN #
1
PIN NAME
vSADR_tri
PIN TYPE
DESCRIPTION
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2 (Bypass
IN
mode) with internal pull up/pull down resistors. See PLL Operating Mode Table for Details.
DNC
DNC
PWR
IN
IN
GND
IN
I/O
PWR
PWR
IN
OUT
OUT
PWR
PWR
OUT
OUT
N/A
IN
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
N/A
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
IN
GND
True clock of differential feedback. The feedback output and feedback input are connected
internally on this pin. Do not connect anything to this pin.
Complement clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
3.3V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominal 3.3V
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
No Connection.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
3.3V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
No Connection.
Power supply, nominal 3.3V
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
Connect paddle to ground.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
^vHIBW_BYPM_LOBW#
FB_DNC
FB_DNC#
VDDR3.3
CLK_IN
CLK_IN#
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG3.3
VDDIO
vOE0#
DIF0
DIF0#
VDD3.3
VDDIO
DIF1
DIF1#
NC
vOE1#
DIF2
DIF2#
vOE2#
VDDA3.3
VDDIO
DIF3
DIF3#
vOE3#
NC
VDD3.3
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDDIO
^CKPWRGD_PD#
ePAD
FEBRUARY 8, 2017
3
6-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL0641 / 9DBL0651 DATASHEET
Test Loads
Low-Power push-pull HCSL Output test load
(integrated terminations)
L inches
Differential Zo
2pF
2pF
Terminations
Device
9DBL0641
9DBL0651
9DBL06P1
9DBL0641
9DBL0651
9DBL06P1
Zo (Ω)
100
100
100
85
85
85
Rs (Ω)
None needed
7.5
Prog.
N/A
None needed
Prog.
L = 5 inches
Alternate Terminations
The 9DBL0641 / 9DBL0651 can easily drive LVPECL, LVDS, and CML logic. See
“AN-891 Driving LVPECL, LVDS, and CML
Logic with IDT's "Universal" Low-Power HCSL Outputs”
for details.
6-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
4
FEBRUARY 8, 2017
9DBL0641 / 9DBL0651 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBL0641 / 9DBL0651. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDx
V
IN
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
MIN
-0.5
TYP
SMBus clock and data pins
-65
Human Body Model
2500
MAX
4.6
V
DD
+0.5
3.9
150
125
UNITS NOTES
V
V
V
°C
°C
V
1,2
1,3
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 4.6V.
Electrical Characteristics–Clock Input Parameters
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Input Crossover Voltage -
DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
SYMBOL
V
CROSS
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
CONDITIONS
Cross Over Voltage
Differential value
Measured differentially
V
IN
= V
DD ,
V
IN
= GND
Measurement from differential wavefrom
Differential Measurement
MIN
150
300
0.4
-5
45
0
TYP
MAX
900
UNITS NOTES
mV
mV
V/ns
uA
%
ps
1
1
1,2
1
1
8
5
55
125
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics–SMBus Parameters
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
1
2.
3.
SYMBOL
V
ILSMB
V
IHSMB
V
OLSMB
I
PULLUP
V
DDSMB
t
RSMB
t
FSMB
f
SMB
CONDITIONS
V
DDSMB
= 3.3V
V
DDSMB
= 3.3V
@ I
PULLUP
@ V
OL
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus operating frequency
MIN
TYP
MAX
0.8
3.6
0.4
3.6
1000
300
500
UNITS NOTES
V
V
V
mA
V
ns
ns
kHz
2.1
4
2.7
1
1
2,3
Guaranteed by design and characterization, not 100% tested in production.
The device must be powered up for the SMBus to function.
The differential input clock must be running for the SMBus to be active
FEBRUARY 8, 2017
5
6-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
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