1:6 LVDS Output 1.8V Fanout Buffer
IDT8P34S1106I
DATA SHEET
General Description
The IDT8P34S1106I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1106I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1106I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. One differential input and six low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the differential device input. The
device is optimized for low power consumption and low additive
phase jitter.
Features
•
•
•
•
•
•
•
•
•
•
Six low skew, low additive jitter LVDS output pairs
One differential clock input pair
Differential CLK, nCLK pair can accept the following differential
input levels: LVDS, CML
Maximum input clock frequency: 1.2GHz (maximum)
Output skew: 20ps (typical)
Propagation delay: 290ps (typical)
Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
12kHz- 20MHz: 39fs (typical)
Full 1.8V supply voltage
Lead-free (RoHS 6), 20-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
V
DD
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q3
16
nQ3
17
Q4
18
nQ4
19
VDD
20
1
2
3
4
5
15
14
13
12
11
10
nQ0
9
Q0
CLK
nCLK
VDD
nQ2
nQ1
Q2
Q1
Top View
8
V
REF
7
nCLK
6
CLK
V
REF
V
REF
Q4
nQ4
Q5
nQ5
GND
nQ5
Q5
IDT8P34S1106I
20-lead VFQFN
4mm x 4mm x 0.925mm package body
2.1mm x 2.1mm ePad Size
NL Package
Top View
IDT8P34S1106NLGI REVISION A JANUARY 22, 2014
1
©2014 Integrated Device Technology, Inc.
V
DD
nc
IDT8P34S1106NLGI Data Sheet
1:6 LVDS Output 1.8V Fanout Buffer
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Note1.
Number
1
2, 3
4
5, 11, 20
6
7
Name
GND
Q5, nQ5
NC
V
DD
CLK
nCLK
Power
Output
Unused
Power
Input
Input
Pulldown
Pulldown/
Pullup
Type
Description
Power supply ground.
Differential output pair 5. LVDS interface levels.
Do not connect.
Power supply pins.
Non-inverting differential clock/data input.
Inverting differential clock/data input.
Bias voltage reference. Provides an input bias voltage for the CLK, nCLK
input pair in AC-coupled applications. Refer to
Figures 2B and 2C
for
applicable AC-coupled input interfaces.
Output
Output
Output
Output
Output
Differential output pair 0. LVDS interface levels.
Differential output pair 1. LVDS interface levels.
Differential output pair 2. LVDS interface levels.
Differential output pair 3. LVDS interface levels.
Differential output pair 4. LVDS interface levels.
8
9, 10
12, 13
14, 15
16, 17
18, 19
1.
V
REF
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
IDT8P34S1106NLGI REVISION A JANUARY 22, 2014
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©2014 Integrated Device Technology, Inc.
IDT8P34S1106NLGI Data Sheet
1:6 LVDS Output 1.8V Fanout Buffer
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model
Note1.
ESD - Charged Device Model
Note 1
1.
According to JEDEC JS-001-2012/JESD22-C101E.
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±2mA
125°C
-65°C to 150°C
2000V
1500V
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Q0 to Q5 terminated 100 between nQx, Qx
Test Conditions
Minimum
1.71
Typical
1.8
100
Maximum
1.89
114
Units
V
mA
IDT8P34S1106NLGI REVISION A JANUARY 22, 2014
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©2014 Integrated Device Technology, Inc.
IDT8P34S1106NLGI Data Sheet
1:6 LVDS Output 1.8V Fanout Buffer
Table 3B. Differential Input Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
Parameter
Input High Current
CLK, nCLK
CLK
Input Low Current
nCLK
V
REF
V
PP
V
CMR
1.
2.
3.
Reference Voltage for Input
Bias
Note1.
Peak-to-Peak Voltage
Note3.
Common Mode Input Voltage
Note2.
Note3.
Test Conditions
V
IN
= V
DD
= 1.89V
V
IN
= 0V, V
DD
= 1.89V
V
IN
= 0V, V
DD
= 1.89V
I
REF
= +100µA, V
DD
= 1.8V
V
DD
= 1.89V
Minimum
Typical
Maximum
150
Units
µA
µA
µA
-10
-150
0.9
0.2
0.9
1.30
1.0
V
DD
– (V
PP
/2)
V
V
V
V
REF
specification is applicable to the AC-coupled input interfaces shown in
Figures 2B and 2C.
Common mode input voltage is defined as crosspoint voltage.
V
IL
should not be less than -0.3V and V
IH
should not be higher than V
DD
.
Table 3C. LVDS DC Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.0
1.23
Test Conditions
Outputs Loaded with 100
Minimum
247
Typical
350
Maximum
454
50
1.4
50
Units
mV
mV
V
mV
IDT8P34S1106NLGI REVISION A JANUARY 22, 2014
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©2014 Integrated Device Technology, Inc.
IDT8P34S1106NLGI Data Sheet
1:6 LVDS Output 1.8V Fanout Buffer
AC Electrical Characteristics
Table 4. AC Electrical Characteristics,
V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Note1.
Symbol
f
REF
V/t
t
PD
tsk(o)
tsk(p)
tsk(pp)
Parameter
Input
Frequency
Input
Edge Rate
CLK, nCLK
Test Conditions
Minimum
Typical
Maximum
1.2
Units
GHz
CLK, nCLK
CLK, nCLK to any Qx, nQx
for V
PP
= 0.4V
1.5
190
290
20
f
REF
= 100MHz
4
400
40
20
250
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 12kHz – 20MHz
10% to 90%
outputs loaded with 100
117
89
85
52
40
39
51
37
36
270
162
221
110
110
107
78
78
112
85
85
400
260
V/ns
ps
ps
ps
ps
fs
fs
fs
fs
fs
fs
fs
fs
fs
ps
ps
Propagation Delay
Note2.
Output Skew
Note3. Note4.
Pulse Skew
Part-to-Part Skew
Note5.
t
JIT
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
t
R
/ t
F
Output Rise/ Fall Time
20% to 80%
outputs loaded with 100
1.
2.
3.
4.
5.
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equi-
librium has been reached under these conditions.
Measured from the differential input crossing point to the differential output crossing point
Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
This parameter is defined in accordance with JEDEC Standard 65.
Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with
equal load conditions. Using the same type of input on each device, the outputs are measured at the differential cross points.
IDT8P34S1106NLGI REVISION A JANUARY 22, 2014
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©2014 Integrated Device Technology, Inc.
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