DS3152N- datasheet, PDF - EEWORLD Datasheet

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DS3152N-: DescriptionTelecom Interface ICs Dual DS3/E3/STS-1 Line Interface Unit; Categorysemiconductor Analog mixed-signal IC; File Size689KB，61 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS3152N- Overview

Telecom Interface ICs Dual DS3/E3/STS-1 Line Interface Unit

DS3152N- Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Maxim
Product Category	Telecom Interface ICs
RoHS	Details
Product	DS3/E3/STS-1 Line Interface Units - LIUs
Supply Voltage - Max	3.465 V
Supply Voltage - Min	3.135 V
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	TE-CSBGA
Packaging	Tube
Data Rate	51.840 Mbps
Number of Channels	2 Channel
Operating Supply Voltage	3.3 V
Factory Pack Quantity	160

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DEMO KIT AVAILABLE

DS3151/DS3152/DS3153/DS3154

Single/Dual/Triple/Quad

DS3/E3/STS-1 LIUs

www.maxim-ic.com

GENERAL DESCRIPTION

The DS3151 (single), DS3152 (dual), DS3153

(triple), and DS3154 (quad) line interface units (LIUs)

perform the functions necessary for interfacing at the

physical layer to DS3, E3, or STS-1 lines. Each LIU

has independent receive and transmit paths and a

built-in jitter attenuator.

FEATURES

Single, Dual, Triple, or Quad Integrated

Transmitter, Receiver, and Jitter Attenuators for

DS3, E3, and STS-1

Each Port Independently Configurable

Perform Receive Clock/Data Recovery and

Transmit Waveshaping

Hardware or CPU Bus Configuration Options

Jitter Attenuators can be Placed in Either the

Receive or Transmit Paths

Interface to 75Ω Coaxial Cable at Lengths Up to

380m (DS3), 440m (E3), or 360m (STS-1)

Use 1:2 Transformers on Tx and Rx

Require Minimal External Components

Local and Remote Loopbacks

Low-Power 3.3V Operation (5V Tolerant I/O)

Industrial Temperature Range: -40°C to +85°C

Small Package: 144-Pin, 13mm x 13mm

Thermally Enhanced CSBGA

RECEIVE

CLOCK

AND DATA

CONTROL

STATUS

TRANSMIT

CLOCK

AND DATA

APPLICATIONS

SONET/SDH and PDH Multiplexers

Digital Cross-Connects

Access Concentrators

ATM and Frame Relay Equipment

Routers

PBXs

DSLAMs

CSUs/DSUs

FUNCTIONAL DIAGRAM

EACH LIU

LINE

DS3, E3,

OR STS-1

RXP

RXN

CLK

DATA

IEEE 1149.1 JTAG Support

Features continued on page 5.

Dallas

Semiconductor

DS315x

ORDERING INFORMATION

PART

DS3151

DS3151N

DS3152

DS3152N

DS3153

DS3153N

DS3154

DS3154N

LIUs

TEMP RANGE

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

PIN-PACKAGE

144 TE-CSBGA

LINE OUT

DS3, E3,

OR STS-1

TXP

TXN

CLK

DATA

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

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REV: 030607

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

TABLE OF CONTENTS

10.

11.

12.

13.

14.

15.

16.

17.

DETAILED DESCRIPTION.................................................................................................5

APPLICATIONS .................................................................................................................7

HARDWARE MODE AND CPU BUS MODE......................................................................8

PIN DESCRIPTIONS ........................................................................................................10

RECEIVER........................................................................................................................22

TRANSMITTER ................................................................................................................25

DIAGNOSTICS .................................................................................................................28

JITTER ATTENUATOR ....................................................................................................29

RESET LOGIC..................................................................................................................30

TRANSFORMERS............................................................................................................31

JTAG TEST ACCESS PORT AND BOUNDARY SCAN ..................................................32

ELECTRICAL CHARACTERISTICS ................................................................................37

PIN ASSIGNMENTS.........................................................................................................46

PACKAGE INFORMATION ..............................................................................................59

THERMAL INFORMATION ..............................................................................................60

REVISION HISTORY ........................................................................................................61

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

LIST OF FIGURES

Figure 1-1. External Connections ...............................................................................................................7

Figure 2-1. 4-Port Unchannelized DS3/E3 Card.........................................................................................7

Figure 3-1. Hardware Mode Block Diagram ...............................................................................................8

Figure 3-2. CPU Bus Mode Block Diagram ................................................................................................9

Figure 5-1. Status Register Logic .............................................................................................................16

Figure 6-1. Receiver Jitter Tolerance .......................................................................................................24

Figure 7-1. E3 Waveform Template .........................................................................................................27

Figure 7-2. DS3 AIS Structure ..................................................................................................................28

Figure 8-1. PRBS Output with Normal RCLK Operation ..........................................................................29

Figure 8-2. PRBS Output with Inverted RCLK Operation .........................................................................29

Figure 9-1. Jitter Attenuation/Jitter Transfer .............................................................................................30

Figure 12-1. JTAG Block Diagram............................................................................................................32

Figure 12-2. JTAG TAP Controller State Machine....................................................................................33

Figure 13-1. Transmitter Framer Interface Timing Diagram .....................................................................38

Figure 13-2. Receiver Framer Interface Timing Diagram .........................................................................39

Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed) ........................................................................41

Figure 13-4. CPU Bus Timing Diagram (Multiplexed)...............................................................................43

Figure 13-5. JTAG Timing Diagram..........................................................................................................45

Figure 14-1. DS3151 Hardware Mode Pin Assignment............................................................................51

Figure 14-2. DS3151 CPU Bus Mode Pin Assignment.............................................................................52

Figure 14-3. DS3152 Hardware Mode Pin Assignment............................................................................53

Figure 14-4. DS3152 CPU Bus Mode Pin Assignment.............................................................................54

Figure 14-5. DS3153 Hardware Mode Pin Assignment............................................................................55

Figure 14-6. DS3153 CPU Bus Mode Pin Assignment.............................................................................56

Figure 14-7. DS3154 Hardware Mode Pin Assignment............................................................................57

Figure 14-8. DS3154 CPU Bus Mode Pin Assignment.............................................................................58

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

LIST OF TABLES

Table 1-A. Applicable Telecommunications Standards ..............................................................................6

Table 4-A. Active I/O Pins—Hardware and CPU Bus Modes...................................................................10

Table 4-B. Transmitter Pin Descriptions ...................................................................................................11

Table 4-C. Receiver Pin Descriptions.......................................................................................................12

Table 4-D. Global Pin Descriptions ..........................................................................................................13

Table 4-E. JTAG and Test Pin Descriptions .............................................................................................14

Table 4-F. Transmitter Data Select Options .............................................................................................14

Table 4-G. Receiver PRBS Pattern Select Options..................................................................................14

Table 5-A. Register Map...........................................................................................................................15

Table 7-A. DS3 Waveform Template........................................................................................................26

Table 7-B. DS3 Waveform Test Parameters and Limits...........................................................................26

Table 7-C. STS-1 Waveform Template ....................................................................................................26

Table 7-D. STS-1 Waveform Test Parameters and Limits .......................................................................27

Table 7-E. E3 Waveform Test Parameters and Limits .............................................................................27

Table 11-A. Transformer Characteristics..................................................................................................31

Table 11-B. Recommended Transformers ...............................................................................................31

Table 12-A. JTAG Instruction Codes ........................................................................................................35

Table 12-B. JTAG ID Code.......................................................................................................................35

Table 13-A. Recommended DC Operating Conditions.............................................................................37

Table 13-B. DC Characteristics ................................................................................................................37

Table 13-C. Framer Interface Timing .......................................................................................................38

Table 13-D. Receiver Input Characteristics—DS3 and STS-1 Modes .....................................................39

Table 13-E. Receiver Input Characteristics—E3 Mode ............................................................................39

Table 13-F. Transmitter Output Characteristics—DS3 and STS-1 Modes ...............................................40

Table 13-G. Transmitter Output Characteristics—E3 Mode .....................................................................40

Table 13-H. CPU Bus Timing ...................................................................................................................40

Table 13-I. JTAG Interface Timing ...........................................................................................................45

Table 14-A. Pin Assignments Sorted by Signal Name .............................................................................46

Table 14-B. Pin Assignments Sorted by Pin Number ...............................................................................48

Table 16-A. Thermal Properties, Natural Convection ...............................................................................60

Table 16-B. Theta-JA (θ

) vs. Airflow ......................................................................................................60

4 of 61

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