NCP308, NCV308
Low Quiescent Current,
Programmable Delay Time,
Supervisory Circuit
The NCP308 series is one of the ON Semiconductor Supervisory
circuit IC families. It is optimized to monitor system voltages from
0.405 V to 5.5 V, asserting an active low open−drain RESET output,
together with Manual Reset (MR) Input. The part comes with both
fixed and externally adjustable versions.
Features
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MARKING
DIAGRAMS
•
Wide Supply Voltage Range 1.6 to 5.5 V
•
Very Low Quiescent Current 1.6
mA
•
Fixed Threshold Voltage Versions for Standard Voltage Rails
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Including 0.9 V, 1.2 V, 1.25 V, 1.5 V, 1.8 V, 1.9 V, 2.5 V, 2.8 V, 3.0 V,
3.3 V, 5.0 V
Adjustable Version with Low Threshold Voltage 0.405 V (min)
High Threshold Voltage Accuracy: 0.31% typ
Support Manual Reset Input ( MR)
Open−Drain RESET Output (Push−pull Output upon Request)
Flexible Delay Time Programmability: 1.25 ms to 10 s
Temperature Range: −40°C to +125°C
Small TSOP−6 and WDFN6 2 x 2 mm, Pb−Free packages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
1
TSOP−6
CASE 318G
1
XXXAYWG
G
WDFN6
CASE 511BR
1
XX M
XXX, XX= Specific Device Code
A
=Assembly Location
Y
= Year
W
= Work Week
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 9 of this data sheet.
Typical Applications
DSP or Microcontroller Applications
Notebook/Desktop Computers
PDAs/Hand−Held Products
Portable/Battery−Powered Products
FPGA/ASIC Applications
VIN
VDD
VIN
VDD
NCP308XXADJ
VDD
R1
SENSE
1 nF
(Optional)
R2
MR
MR
GND
CT
RESET
Rpullup
RESET
DSP/
Processor
SENSE
CT
(Optional)
MR
MR
GND
CT
VDD
RESET
Rpullup
RESET
DSP/
Processor
CT
(Optional)
Figure 1. Typical Application Circuit for Adjustable
Versions
Figure 2. Typical Application Circuit for Fixed
Versions
©
Semiconductor Components Industries, LLC, 2014
1
December, 2014 − Rev. 6
Publication Order Number:
NCP308/D
NCP308, NCV308
VDD
VDD
NCP308SNADJ/NCP308MTADJ
Adjustable Versions
VDD
VDD
NCP308SNXXX/NCP308MTXXX
Fixed Versions
90k
MR
CT
MR
90k
CT
SENSE
−
+
RESET
Control Logic
and Timer
SENSE
R1
−
+
RESET
Control Logic
and Timer
Vref
R2
Vref
GND
Figure 3. Functional Block Diagrams of Adjustable and Fixed Versions
RESET
1
6
VDD
VDD
1
6
RESET
GND
2
GND
5
SENSE
SENSE
2
5
GND
CT
MR
3
4
CT
3
4
MR
Figure 4. Pin Connections Diagram (Top View)
Table 1. PIN OUT DESCRIPTION
Pin Number
Name
VDD
SENSE
TSOP−6
6
5
WDFN6
1
2
Description
Supply Voltage.
A 0.1uF ceramic capacitor placed close to this pin is helpful for transient and
parasitic.
Sense Input,
this is the voltage to be monitored. If the voltage at this terminal drops below the
threshold voltage V
IT
, then RESET is asserted. SENSE does not necessary monitor VDD, it can
monitor any voltage lower than VDD.
Reset Delay Time Setting Pin.
Connecting this pin to VDD through a 40 kW to 200 kW resistor or
leaving it open results in fixed reset delay times. Connecting this pin to a ground referenced
capacitor (≥ 100 pF) gives a user−programmable reset delay time. See the
Setting Reset Delay
Time
section for more information.
Manual Reset input,
MR low asserts RESET. MR is internally tied to VDD by a 90 kW pull−up
Resistor.
RESET Output,
is an Active low open drain N−Channel MOSFET output, it is driven to a low
impedance state when RESET is asserted (either the SENSE input is lower than the threshold
voltage (V
IT
) or the MR pin is set to a logic low). RESET will keep low (asserted) for the reset
delay time after both SENSE is above V
IT
and MR is set to a logic high. A pull−up resistor from
10kW to 1MW should be used on this pin. See Figure 5 for behavior of RESET depends on VDD,
SENSE and MR conditions.
Ground terminal.
Should be connected to PCB ground reference
Exposed pad,
under WDFN6 package, connect it to ground plane for better thermal dissipation.
CT
4
3
MR
RESET
3
1
4
6
GND
EXP
PAD
2
−
5
Exposed
Pad
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NCP308, NCV308
Uncertain State
V
DD
V
DD(min)
0.0 V
RESET
tD
SENSE
tP2
tD
V
IT
+ V
HYS
V
IT
tP1
MR
0.7 V
DD
0.3 V
DD
tD
Figure 5. Timing Diagram Showing MR and SENSE Reset Timing
Table 2. TRUTH TABLE
MR
L
L
H
H
SENSE > V
IT
N
Y
N
Y
RESET
L
L
L
H
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NCP308, NCV308
Table 3. MAXIMUM RATINGS
Rating
Input voltage range, V
DD
CT voltage range V
CT
, RESET, MR
Current through CT pin
SENSE pin voltage
RESET pin current
Thermal Resistance Junction−to−Air
TSOP−6
WDFN6
Human Body Model (HBM) ESD Rating (Note 1)
Machine Model (MM) ESD Rating (Note 1)
Charged Device Model (CDM) ESD Rating (Note 1)
Latch up Current: (Note 2)
All pins, except digital pins
Digital pins (MR)
Storage Temperature Range
Maximum Junction Temperature
Moisture Sensitivity (Note 3)
R
qJA
Symbol
V
DD
I
CT
Value
−0.3 to + 6.0
−0.3 to V
DD
+0.3
≤
6.0
10
−0.3 to + 8.0
5
305
220
2000
100
500
±100
±10
−65 to + 150
−40 to +150
Level 1
V
V
V
mA
Unit
V
V
mA
V
mA
°C/W
ESD HBM
ESD MM
ESD CDM
I
LU
T
STG
T
J
MSL
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) +/−2.0 kV per JEDEC standard: JESD22−A114
Machine Model (MM) +/−100 V per JEDEC standard: JESD22−A115
Charged Device Model (CDM) 500 V per JEDEC standard: JESD22−C101.
2. Latch up Current per JEDEC standard: JESD78 class II.
3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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NCP308, NCV308
Table 4. ELECTRICAL CHARACTERISTICS
1.6 V
≤
V
DD
≤
5.5 V, R
pullup
= 100 kW, C
LRESET
= 50 pF, over operating
temperature range (T
J
= −40°C to +125°C), unless otherwise specified. Typical values are at T
J
= +25°C.
Symbol
V
DD
V
DD
(min)
I
DD
Parameter
Supply Voltage Range
Minimum V
DD
Guaranteed RESET
Output Valid (Note 4)
Supply Current (Current into VDD
pin)
V
DD
= 3.3V, RESET not asserted
MR, RESET, CT open
V
DD
= 5.5V, RESET not asserted
MR, RESET, CT open
V
OL
Low−level output voltage of RESET
1.3V
≤
V
DD
< 1.6V, I
OL
= 0.4 mA
1.6V
≤
V
DD
≤
5.5V, I
OL
= 1.0 mA
V
IT
%
Negative going SENSE threshold
voltage accuracy
−1.75
T
J
= +25°C
−20°C < T
J
< +85°C
V
HYS
Hysteresis on
V
IT
1.6V≤V
DD
≤4.2V
4.2V≤V
DD
≤5.5V
−0.31
−1.0
±0.75
−
±0.5
1.0
1.75
90
V
SENSE
= V
IT
V
SENSE
= 5.5 V
V
RESET
= 5.5 V, RESET not
asserted
V
IN
= 0 V to V
DD
V
IN
= 0 V to 5.5 V
0
0.7 V
DD
SENSE
MR
C
T
= Open
C
T
= V
DD
C
T
= 100 pF
C
T
= 180 nF
MR to RESET
SENSE to
RESET
V
IH
= 1.05 V
IT
, V
IL
= 0.95 V
IT
V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
(Guaranteed by design and
characterization)
20
150
20
300
1.25
1200
150
20
ms
5
5
0.3 V
DD
V
DD
V
V
ms
Conditions
−40°C < T
J
< +125°C
Min
1.6
0.5
1.6
1.6
Typ
Max
5.5
0.8
5.0
6.0
0.3
0.4
+1.75
0.31
+1.0
3.0
3.75
kW
nA
%V
IT
%
V
Unit
V
V
mA
R
MR
I
SENSE
MR Internal pull−up resistance
Input current at
SENSE pin
NCP308XXADJ
Fixed versions
10
110
300
I
OH
C
IN
RESET leakage Current
Input
capacitance, any
pin
MR logic low input
MR logic high input
Input pulse width
to assert RESET
Reset delay time
CT pin
Other pins
nA
pF
V
IL
V
IH
tw
t
D
t
P1
t
P2
Propagation
delay from MR
Propagation
delay from
SENSE
V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
V
IH
= 1.05 V
IT
, V
IL
= 0.95 V
IT
ns
ms
4. The lowest supply voltage (V
DD
) at which RESET becomes active.
5. NCP308XX: XX = MT (WDFN6 package) or SN (TSOP−6 package).
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