S75NS-N
S29NS-N: MirrorBit
™
1.8 Volt-only Simultaneous Read/
Write, Burst-mode Multiplexed Flash (NOR Interface)
S30MS-P: ORNAND
™
Flash (NAND interface)
Multiplexed Synchronous pSRAM
Data Sheet
(Advance Information)
S75NS-N Cover Sheet
Notice to Readers:
This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See
Notice On Data Sheet Designations
for definitions.
Publication Number
S75NS-N_00
Revision
01E
Issue Date
May 3, 2006
Data
Sheet
(Adva nce
In fo rma tio n)
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
LLC therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion LLC.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion LLC reserves the right to change or discontinue work on this
proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V
IO
range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion LLC applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion LLC deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical
or specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
ii
S75NS-N
May 3, 2006 S75NS-N_00-01E
S75NS-N
S29NS-N: MirrorBit
™
1.8 Volt-only Simultaneous Read/
Write, Burst-mode Multiplexed Flash (NOR Interface)
S30MS-P: ORNAND
™
Flash (NAND interface)
Multiplexed Synchronous pSRAM
Data Sheet
(Advance Information)
Features
Power supply voltage of 1.7 V to 1.95 V
Burst Speed: 66 MHz
Package - MCP BGA: 0.5 mm ball pitch
– 11 x 13 x 1.4 mm, 112 ball
Operating Temperature
– Wireless, –25°C to +85°C
General Description
The S75NS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items:
S29NS-N
S30MS-P
Mux pSRAM
The products covered by this document are listed in the tables below.
pSRAM
S29NS128 +
S30MS512P
S30MS01GP
32 Mb
S75NS128NBF
S75NS128NBG
Product Selector Guide
Device
S75NS128NBF
S75NS128NBG
pSRAM Density
32 Mb
32 Mb
pSRAM Type
Multiplexed pSRAM Type 3
Multiplexed pSRAM Type 3
For detailed specifications, please refer to the individual data sheets:
Document
S29NS-N
S30MS-P
32 Mb Multiplexed pSRAM Type 3
Publication Identification Number
S29NS-N_00
S30MS-P_00
muxpsram_04
Publication Number
S75NS-N_00
Revision 01E
Issue Date
May 3, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design
in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Data
Sheet
(Adva nce
In fo rma tio n)
1.
Ordering Information
The ordering part number is formed by a valid combination of the following:
S75NS 128
N
B
G
J
W
JZ
0
Packing Type
0 = Tray
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
Model Number
Refer to the Valid Combinations table below
Temperature Range
W = Wireless (-25°C to +85°C)
Package Type
J = 1.4 mm height, 0.5mm ball size, Thin Fine-Pitch Ball Grid
Array (FBGA) Lead (Pb)-free Package (LF35)
ORNAND Data Density
F = 512 Mb
G = 01 Gb
pSRAM Density
B = 32 Mb
C = 64 Mb
Process Technology
N = 110 nm MirrorBit Technology
Flash Density
256 = 256 Mb
128 = 128 Mb
Device Family
S75NS = Multi-Chip Product 1.8 Volt-only Simultaneous Read/
Write Burst Mode Multiplexed Flash Memory + pSRAM +
ORNAND Data Storage
1.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Table 1.1
MCP Configurations and Valid Combinations
Base Ordering Part
Number (Note 2)
S75NS128NBF
UJW
S75NS128NBG
JZ
Package &
Temperature
Model
Number
JZ
0, 2, 3
pSRAM Type 3
66 MHz
66 MHz
Packing
Type
pSRAM Type
pSRAM Type 3
Flash Speed
Options
66 MHz
pSRAM Speed
Options
66 MHz
Notes:
1. Type 0 is standard. Specify other options as required.
2. The package marking omits the leading
S
and packing type designator from the ordering part number.
3. Contact factory for availability of any of the OPNs listed because RAM type availability may vary over time.
2
S75NS-N
S75NS-N_00_01E May 3, 2006
Da ta
Shee t
(Advance
I nformation)
2.
Input/Output Descriptions
Table 2.1
identifies the input and output package connections provided on the device.
Table 2.1
Input/Output Descriptions
Symbol
AMAX – A16
ADQ15 – ADQ0
OE#
WE#
V
SS
F-RDY / R-WAIT
Signal
Type
Input
I/O
Input
Input
Ground
Output
Address inputs
Multiplexed Address/Data
Output Enable input. Asynchronous relative to CLK for the Burst
mode.
Write Enable input.
Ground
Ready output. Indicates the status of the Burst read. The WAIT#
pin of the pSRAM is tied to RDY.
Clock input. In burst mode, after the initial word is output,
subsequent active edges of CLK increment the internal address
counter. Should be at V
IL
or V
IH
while in asynchronous mode
Address Valid input. Indicates to device that the valid address is
present on the address inputs. Low = for asynchronous mode,
indicates valid address; for burst mode, causes starting address
to be latched. High = device ignores address inputs
Hardware reset input. Low = device resets and returns to reading
array data
Hardware write protect input. At V
IL
, disables program and erase
functions in the four outermost sectors. Should be at V
IH
for all
other conditions.
Accelerated input. At V
HH
, accelerates programming;
automatically places device in unlock bypass mode. At V
IL
,
disables all program and erase functions. Should be at V
IH
for all
other conditions.
Chip-enable input for Flash. Asynchronous relative to CLK for
Burst Mode.
Flash 1.8 Volt-only single power supply
Chip-enable input for pSRAM
Control Register Enable (pSRAM)
pSRAM Power Supply
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Command Latch Enable
Address Latch Enable
Chip Enable input for ORNAND
Write Enable input
Read Enable input
Data Input/Output
Hardware write protect input. At V
IL
, disables program and erase
functions in the four outermost sectors. Should be at V
IH
for all
other conditions.
Ready/Busy output
Power-On Read Enable
Ground
ORNAND 1.8 Volt-only single power supply.
Do Not Use
No Connect; not connected internally
Description
NS
(NOR)
X
X
X
X
X
X
pSRAM
X
X
X
X
X
X
MS
(ORNAND)
CLK
Input
X
X
AVD#
Input
X
X
F-RST#
Input
X
F-WP#
Input
X
F-ACC
Input
X
F-CE#
V
CC
R-CE1#
R-CRE
R-V
CC
R-UB#
R-LB#
N-CLE
N-ALE
N-CE#
N-WE#
N-RE#
N-IO0 - N-IO7
N-WP#
N-RY/BY#
N-PRE
N-V
SS
N-V
CC
DNU
NC
Input
Power
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
I/O
Input
Input
Input
Ground
Power
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S75NS-N_00_01E May 3, 2006
S75NS-N
3
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