5962-8961404YX datasheet, PDF - EEWORLD Datasheet

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5962-8961404YX: DescriptionUVPROM, 128KX8, 300ns, CMOS, CDIP32,; Categorystorage storage; File Size139KB，24 Pages; ManufacturerWaferscale Integration Inc.

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5962-8961404YX Overview

UVPROM, 128KX8, 300ns, CMOS, CDIP32,

5962-8961404YX Parametric

Parameter Name	Attribute value
Maker	Waferscale Integration Inc.
Reach Compliance Code	unknown
Maximum access time	300 ns
JESD-609 code	e0
memory density	1048576 bit
Memory IC Type	UVPROM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX8
Package body material	CERAMIC, GLASS-SEALED
Package form	IN-LINE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal location	DUAL
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Updated boilerplate. Added device types 13-16. glg

Revision in accordance with NOR 5962-R069-99. glg

Add devices 17 – 20. This revision addresses programming

interchangeability issue as a result of revision E, NOR 5962-R069-

99. Figure 2, Truth table; will be modified to add a second truth table

for devices 17 – 20. This change indicates devices which require V

to be tied to V

, from those devices which may be tied to either V

as was previously the requirement prior to revision E. ksr

Update to paragraphs, part of regular review cycle. ksr

DATE (YR-MO-DA)

95 – 12 – 15

99 – 08 – 04

APPROVED

Michael Frye

Raymond Monnin

03 – 02 – 05

Raymond Monnin

09-02-18

Robert M. Heber

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

James E. Jamison

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

CHECKED BY

Raymond Monnin

APPROVED BY

Michael A. Frye

DRAWING APPROVAL DATE

95 – 12 – 15

REVISION LEVEL

MICROCIRCUIT, MEMORY,

DIGITAL, CMOS, 128K X 8-BIT

UVEPROM, MONOLITHIC

SILICON

SIZE

SHEET

1 OF

5962-E180-09

CAGE CODE

67268

5962-89614

DSCC FORM 2233

APR 97

ELECTRONICS INDUSTRIES ASSOCIATION (EIA)

JEDEC Standard EIA/JESD78

IC Latch-Up Test.

(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA

22201;

http://www.jedec.org.)

(Non-Government standards and other publications are normally available from the organizations that prepare or distribute

the documents. These documents also may be available in or through libraries or other informational services.)

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless

a specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Truth table. The truth table shall be as specified on figure 2.

3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing

shall be as specified on figure 2 herein. When required, in screening (see 4.2 herein), or quality conformance inspection

groups A, B, C, or D (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test in a checkerboard or

similar pattern (a minimum of 50 percent of the total number of bits programmed).

3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this document.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the

full case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table IA.

3.5 Processing EPROM's. All testing requirements and quality assurance provisions herein shall be satisfied by the

manufacturer prior to delivery.

3.5.1 Erasure of EPROM's. When specified, devices shall be erased in accordance with the procedure and characteristics

specified in 4.5 herein.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-89614

SHEET

3.5.2 Programmability of EPROM's. When specified, devices shall be programmed to the specified pattern using the

procedures and characteristics specified in 4.6 herein.

3.5.3 Verification of erasure of programmability of EPROM's. When specified, devices shall be verified as either

programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test

(subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a

device failure, and shall be removed from the lot.

3.6 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

3.6.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.7 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535

and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.8 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for

device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.9 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.10 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain

the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.11 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 42 (see MIL-PRF-38535, appendix A).

3.12 Substitution. Substitution data shall be as indicated in appendix A herein.

3.13 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitors. This

reprogrammability test shall be done for initial characterization and after any design or process changes which may affect the

reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of

program/erase endurance cycles listed in section 1.3 herein over the full military temperature range. The vendor's procedure

shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with

test data.

3.14 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test

shall be done for initial characterization and after any design or process change which may affect data retention. The methods

and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein, over the full

military temperature range. The vendor's procedure shall be kept under document control and shall be made available upon

request by the preparing or acquiring activity, along with the test data.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-89614

SHEET

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