Data Sheet
FEATURES
4.7 Ω maximum on resistance at 25°C
0.5 Ω on-resistance flatness
Fully specified at ±15 V/+12 V/±5 V
3 V logic-compatible inputs
Up to 115 mA continuous current per channel
Rail-to-rail operation
Break-before-make switching action
16-/20-lead TSSOP and 4 mm × 4 mm LFCSP
4 Ω R
ON
, Triple/Quad SPDT
±15 V/+12 V/±5 V
iCMOS
Switches
ADG1433/ADG1434
FUNCTIONAL BLOCK DIAGRAMS
ADG1433
S1A
D1
S1B
S3B
D3
S2B
D2
S2A
LOGIC
S3A
APPLICATIONS
Relay replacement
Audio and video routing
Automatic test equipment
Data acquisition systems
Temperature measurement systems
Avionics
Battery-powered systems
Communication systems
Medical equipment
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
06181-001
Figure 1.
ADG1433
TSSOP and LFCSP
ADG1434
S1A
D1
S1B
IN1
IN2
S2B
D2
S2A
S4A
D4
S4B
IN4
IN3
S3B
D3
S3A
GENERAL DESCRIPTION
The
ADG1433
and
ADG1434
are monolithic industrial CMOS
(iCMOS®) analog switches comprising three independently
selectable single-pole, double-throw (SPDT) switches and
four independently selectable SPDT switches, respectively.
All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An EN
input on the
ADG1433
(LFCSP and TSSOP) and
ADG1434
(LFCSP only) enables or disables the device. When disabled, all
channels are switched off.
The
iCMOS
modular manufacturing process combines high
voltage, complementary metal-oxide semiconductor (CMOS),
and bipolar technologies. It enables the development of a wide
range of high performance analog ICs capable of 33 V operation
in a footprint that no other generation of high voltage devices
has been able to achieve. Unlike analog ICs using a conventional
CMOS process,
iCMOS
components can tolerate high supply
voltages while providing increased performance, dramatically
lower power consumption, and reduced package size.
The ultralow on resistance and on resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications, where low distortion is critical.
iCMOS
construction ensures ultralow power dissipation, making the
devices ideally suited for portable and battery-powered
instruments.
Rev. E
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
Figure 2.
ADG1434
TSSOP
ADG1434
S1A
D1
S1B
S2B
D2
S2A
LOGIC
S4A
D4
S4B
S3B
D3
S3A
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
Figure 3.
ADG1434
LFCSP
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
06181-101
IN1 IN2 IN3 IN4 EN
06181-002
ADG1433/ADG1434
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
12 V Single Supply ........................................................................ 5
±5 V Dual Supply ......................................................................... 6
Data Sheet
Absolute Maximum Ratings ............................................................7
Thermal Resistance .......................................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ........................................... 10
Test Circuits..................................................................................... 13
Terminology .................................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 17
REVISION HISTORY
8/2016—Rev. D to Rev. E
Changes to Analog Inputs Parameter and Digital Inputs
Parameter, Table 4.............................................................................. 7
3/2016—Rev. C to Rev. D
Changed CP-20-4 to CP-20-10 and CP-16-13 to
CP-16-26 ......................................................................... Throughout
Changes to Figure 5 and Table 6 ..................................................... 8
Changes to Figure 6, Figure 7, and Table 8 ................................... 9
Changes to Figure 27 ...................................................................... 13
Changes to Figure 31, Figure 32, and Figure 33 ......................... 14
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
6/2009—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
3/2009—Rev. A to Rev. B
Change to I
DD
Parameter, Table 1 ....................................................4
Change to I
DD
Parameter, Table 2 ....................................................5
Updated Outline Dimensions, Figure 39 .................................... 17
6/2008—Rev. 0 to Rev. A
Added Continuous Current per Channel Parameter, Table 1 .....4
Added Continuous Current per Channel Parameter, Table 2 .....5
Added Continuous Current per Channel Parameter, Table 3 .....6
Changes to Table 4.............................................................................7
Changes to Figure 30...................................................................... 13
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
10/2006—Revision 0: Initial Version
Rev. E | Page 2 of 20
Data Sheet
SPECIFICATIONS
±15 V DUAL SUPPLY
V
DD
= +15 V ± 10%, V
SS
= –15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, R
ON
On Resistance Match Between
Channels, ΔR
ON
On Resistance Flatness, R
FLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off )
Drain Off Leakage, I
D
(Off )
Channel On Leakage, I
D
, I
S
(On)
DIGITAL INPUTS
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current, I
IL
or I
IH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
2
Transition Time, t
TRANS
Break-Before-Make Time Delay, t
D
t
ON
(EN)
t
OFF
(EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion, THD + N
−3 dB Bandwidth
Insertion Loss
C
S
(Off )
C
D
(Off )
C
D
, C
S
(On)
+25°C
−40°C to
+85°C
−40°C to
+125°C
1
V
SS
to V
DD
4
4.7
0.5
0.78
0.5
0.72
±0.04
±0.3
±0.04
±0.3
±0.05
±0.4
5.7
0.85
0.77
6.7
1.1
0.92
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
ADG1433/ADG1434
Test Conditions/Comments
V
S
= ±10 V, I
S
= −10 mA; see Figure 25
V
DD
= +13.5 V, V
SS
= −13.5 V
V
S
= ±10 V, I
S
= −10 mA
V
S
= ±10 V, I
S
= −10 mA
V
DD
= +16.5 V, V
SS
= −16.5 V
V
D
= ±10 V, V
S
= ±10 V; see Figure 26
V
D
= ±10 V, V
S
= ±10 V; see Figure 26
V
S
= V
D
= ±10 V; see Figure 27
±0.6
±0.6
±0.8
±3
±3
±8
2.0
0.8
±0.005
±0.1
3
140
170
40
140
170
60
75
−50
−70
−70
0.025
200
0.24
12
22
72
V
IN
= V
GND
or V
DD
200
230
30
200
85
230
90
R
L
= 100 Ω, C
L
= 35 pF
V
S
= 10 V, see Figure 28
R
L
= 100 Ω, C
L
= 35 pF
V
S1
= V
S2
= 10 V, see Figure 29
R
L
= 100 Ω, C
L
= 35 pF
V
S
= 10 V, see Figure 30
R
L
= 100 Ω, C
L
= 35 pF
V
S
= 10 V, see Figure 30
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF, see Figure 31
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 32
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 34
R
L
= 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz, see
Figure 35
R
L
= 50 Ω, C
L
= 5 pF, see Figure 33
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 33
f = 1 MHz
f = 1 MHz
f = 1 MHz
Rev. E | Page 3 of 20
ADG1433/ADG1434
Parameter
POWER REQUIREMENTS
I
DD
I
DD
I
SS
V
DD
/V
SS
Continuous Current per Channel
2
ADG1433
ADG1434
1
2
Data Sheet
+25°C
0.001
1
260
475
0.001
1
±4.5/±16.5
115
100
75
65
40
40
−40°C to
+85°C
−40°C to
+125°C
1
Unit
µA typ
µA max
µA typ
µA max
µA typ
µA max
V min/max
mA max
mA max
Test Conditions/Comments
V
DD
= +16.5 V, V
SS
= −16.5 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
Digital inputs = 0 V, 5 V, or V
DD
GND = 0 V
V
DD
= +13.5 V, V
SS
= −13.5 V
Temperature range for Y version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. E | Page 4 of 20
Data Sheet
12 V SINGLE SUPPLY
V
DD
= 12 V ± 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, R
ON
On Resistance Match Between
Channels, ΔR
ON
On Resistance Flatness, R
FLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off)
Drain Off Leakage, I
D
(Off)
Channel On Leakage, I
D
, I
S
(On)
DIGITAL INPUTS
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current, I
IL
or I
IH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
2
Transition Time, t
TRANS
Break-Before-Make Time Delay, t
D
t
ON
(EN)
t
OFF
(EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
Insertion Loss
C
S
(Off)
C
D
(Off)
C
D
, C
S
(On)
POWER REQUIREMENTS
I
DD
I
DD
V
DD
Continuous Current per Channel
2
+25°C
−40°C to
+85°C
−40°C to
+125°C
1
0 to V
DD
6
8
0.55
0.82
1.5
2.5
±0.04
±0.3
±0.04
±0.3
±0.06
±0.4
9.5
0.85
2.5
11.2
1.1
2.8
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
µA typ
µA max
µA typ
µA max
V min/max
mA max
mA max
ADG1433/ADG1434
Test Conditions/Comments
V
S
= 0 V to 10 V, I
S
= −10 mA, see Figure 25
V
DD
= 10.8 V, V
SS
= 0 V
V
S
= 0 V to 10 V, I
S
= −10 mA
V
S
= 0 V to 10 V, I
S
= −10 mA
V
DD
= 13.2 V
V
S
= 1 V/10 V, V
D
= 10 V/1 V, see Figure 26
V
S
= 1 V/10 V, V
D
= 10 V/1 V, see Figure 26
V
S
= V
D
= 1 V or 10 V, see Figure 27
±0.6
±0.6
±0.8
±3
±3
±8
2.0
0.8
±0.005
±0.1
4
200
255
80
210
270
70
86
−10
–70
–70
135
0.5
25
45
80
0.002
1
260
475
5/16.5
100
85
65
60
40
35
V
IN
= V
GND
or V
DD
310
350
55
320
95
360
105
R
L
= 100 Ω, C
L
= 35 pF
V
S
= 8 V, see Figure 28
R
L
= 100 Ω, C
L
= 35 pF
V
S1
= V
S2
= 8 V, see Figure 29
R
L
= 100 Ω, C
L
= 35 pF
V
S
= 8 V, see Figure 30
R
L
= 100 Ω, C
L
= 35 pF
V
S
= 8 V, see Figure 30
V
S
= 6 V, R
S
= 0 Ω, C
L
= 1 nF, see Figure 31
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 32
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 34
R
L
= 50 Ω, C
L
= 5 pF, see Figure 33
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 33
f = 1 MHz
f = 1 MHz
f = 1 MHz
V
DD
= 13.2 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
V
SS
= 0 V, GND = 0 V
V
DD
= +10.8 V, V
SS
= 0 V
ADG1433
ADG1434
1
2
Temperature range for Y version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. E | Page 5 of 20
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