CS5422
Dual Out−of−Phase
Synchronous
Buck Controller
with Current Limit
The CS5422 is a dual N−channel synchronous buck regulator
controller. It contains all the circuitry required for two independent
buck regulators and utilizes the V
2
™
control method to achieve the
fastest possible transient response and best overall regulation, while
using the least number of external components. The CS5422 features
out−of−phase synchronization between the channels, reducing the
input filter requirement. The CS5422 also provides undervoltage
lockout, Soft Start, built in adaptive FET non−overlap and hiccup
mode overcurrent protection. The part is available in a 16 Lead SO
Narrow or 24 Lead Fused SO Wide package allowing the designer to
minimize solution size.
Features
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SO−16
D SUFFIX
CASE 751B
1
SO−24L
DWF SUFFIX
CASE 751E
1
16
24
PIN CONNECTIONS AND
MARKING DIAGRAMS
GATE(H)1
GATE(L)1
GND
BST
IS+1
IS−1
V
FB1
COMP1
1
SO−16
16
GATE(H)2
GATE(L)2
V
CC
R
OSC
IS+2
IS−2
V
FB2
COMP2
•
•
•
•
•
•
•
•
Control Topology
Hiccup Mode Overcurrent Protection
150 ns Transient Response
Programmable Soft Start
100% Duty Cycle for Enhanced Transient Response
150 kHz to 600 kHz Programmable Frequency Operation
Switching Frequency Set by Single Resistor
Out−Of−Phase Synchronization Between the Channels Reduces the
Input Filter Requirement
•
Undervoltage Lockout
•
Internally Fused Leads available in 24 Lead SO Wide Package
V
2
GATE(H)1
GATE(L)1
PGND
BST
LGND
LGND
LGND
LGND
IS+1
IS−1
V
FB1
COMP1
A
WL, L
YY, Y
WW, W
1
SO−24L
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
CS5422GD16
CS5422GDR16
CS5422GDWF24
CS5422GDWFR24
©
Semiconductor Components Industries, LLC, 2006
Package
SO−16
SO−16
SO−24L
SO−24L
CS5422
AWLYWW
AWLYYWW
CS5422
24
GATE(H)2
GATE(L)2
V
CC
R
OSC
LGND
LGND
LGND
LGND
IS+2
IS−2
V
FB2
COMP2
Shipping
48 Units/Rail
2500 Tape & Reel
31 Units/Rail
1000 Tape & Reel
July, 2006
−
Rev. 7
1
Publication Order Number:
CS5422/D
12 V
D1
D2
MMSD914T1
+
C1
+
C2
Q5
2N3904
220
D3
BZX84C18LT1
C5
0.1
μF
C4
0.1
μF
220
μF
220
μF
R10
C3
C16
1.0
μF
U1
L2
+
R21
10
1.0
μF
V
CC
BST
GATE(H)1
0
R17
0
Q2
R14
Q1 MTD3302
L1
1.3
μH/15
A
MTD3302
+
+
1.5 V/10 A
1.3
μH/15
A
Q4
MTD3302
R3 4 k
C7
0.1
μF
R4
4k
C15
0.1
μF
IS−2
COMP2
IS+2
CS5422
0
GATE(L)2
IS+1
R2
IS−1
COMP1
4k
GATE(L)1
R18
MTD3302
0
C13
680
μF/
4V
CS5422
Q3
GATE(H)2
R13
Figure 1. Demonstration Circuit Schematic
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V
FB2
R
OSC
R19
0
C21
CAP NP
R9
30.9 k
GND
V
FB1
C22
CAP NP
R8
10 k
±
1%
2
1.8 V/10 A
C8
680
μF/
4V
R1 4 k
C6
0.1
μF
C9
680
μF/
4V
+
C11
680
μF/
4V
+
C12
680
μF/
4V
+
C10
680
μF/
4V
R7
C14
0.1
μF
R5
R20
0
R6
10 k
±
1%
8 k
±
1%
5 k
±
1%
CS5422
ABSOLUTE MAXIMUM RATINGS*
Rating
Operating Junction Temperature, T
J
Storage Temperature Range, T
S
ESD Susceptibility (Human Body Model)
Package Thermal Resistance, SO−16:
Junction−to−Case, R
θJC
Junction−to−Ambient, R
θJA
Package Thermal Resistance, SO−24L:
Junction−to−Case, R
θJC
Junction−to−Ambient, R
θJA
Lead Temperature Soldering:
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Reflow: (SMD styles only) (Note 1)
Value
150
−65
to +150
2.0
28
115
9.0
55
230 peak
Unit
°C
°C
kV
°C/W
°C/W
°C/W
°C/W
°C
ABSOLUTE MAXIMUM RATINGS
Pin Symbol
V
CC
COMP1, COMP2
V
FB1
, V
FB2
BST
R
OSC
GATE(H)1
,
GATE(H)2
GATE(L)1
,
GATE(L)2
GND
IS+1, IS+2
IS−1, IS−2
Pin Name
IC Power Input
Compensation Capacitor for
Channel 1 or 2
Voltage Feedback Input for
Channel 1 or 2
Power Input for GATE(H)1, 2
Oscillator Resistor
High−Side FET Driver
for Channel 1 or 2
Low−Side FET Driver for
Channel 1 or 2
Ground
Positive Current Sense for
Channel 1 or 2
Negative Current Sense for
Channel 1 or 2
V
MAX
16 V
4.0 V
5.0 V
20 V
4.0 V
20 V
16 V
0V
6.0 V
6.0 V
V
MIN
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
−0.3
V
0V
−0.3
V
−0.3
V
I
SOURCE
N/A
1.0 mA
1.0 mA
N/A
1.0 mA
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
1.0 mA
1.0 mA
I
SINK
1.5 A peak
200 mA DC
1.0 mA
1.0 mA
1.5 A peak
200 mA DC
1.0 mA
1.5 A peak
200 mA DC
1.5 A peak
200 mA DC
N/A
1.0 mA
1.0 mA
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3
CS5422
ELECTRICAL CHARACTERISTICS
(0°C < T
A
< 70°C; 0°C < T
J
< 125°C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1
μF,
10.8 V < V
CC
< 13.2 V; 10.8 V < BST < 20 V, C
GATE(H)1,2
= C
GATE(L)1,2
= 1.0 nF, unless otherwise specified.)
Characteristic
Error Amplifier
V
FB1(2)
Bias Current
V
FB1(2)
Input Range
COMP1,2 Source Current
COMP1,2 Sink Current
Reference Voltage 1(2)
COMP1,2 Max Voltage
COMP1,2 Min Voltage
Open Loop Gain
Unity Gain Band Width
PSRR @ 1.0 kHz
Transconductance
Output Impedance
GATE(H) and GATE(L)
High Voltage (AC)
Low Voltage (AC)
Rise Time
Measure: V
CC
−
GATE(L)1,2;
BST
−
GATE(H)1,2; Note 2
Measure:GATE(L)1,2 or GATE(H)1,2; Note 2
1.0 V < GATE(L)1,2 < V
CC
−
1.0 V
1.0 V < GATE(H)1,2 < BST
−
1.0 V,
BST
≤
14 V
V
CC
−
1.0 > GATE(L)1,2 > 1.0 V
BST
−
1.0 > GATE(H)1,2 > 1.0 V,
BST
≤
14 V
GATE(H)1,2 < 2.0 V, GATE(L)1,2 > 2.0 V
BST
≤
14 V
GATE(L)1,2 < 2.0 V, GATE(H)1,2 > 2.0 V;
BST
≤
14 V
Resistance to GND
Note 2
−
−
−
0
0
20
0.5
0.5
50
V
V
ns
V
FB1(2)
= 0 V
−
COMP1,2 = 1.2 V to 2.5 V; V
FB1(2)
= 0.8 V
COMP1,2 = 1.2 V; V
FB1(2)
= 1.2 V
COMP1 = V
FB1
; COMP2 = V
FB2
V
FB1(2)
= 0.8 V
V
FB1(2)
= 1.2 V
−
−
−
−
−
−
0
15
15
0.980
3.0
−
−
−
−
−
−
0.5
−
30
30
1.000
3.3
0.25
95
40
70
32
2.5
1.6
1.1
60
60
1.020
−
0.35
−
−
−
−
−
μA
V
μA
μA
V
V
V
dB
kHz
dB
mmho
MΩ
Test Conditions
Min
Typ
Max
Unit
Fall Time
−
15
50
ns
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE(H)1(2) and GATE(L)1(2)
pull−down.
PWM Comparator
Transient Response
PWM Comparator Offset
Artificial Ramp
Minimum Pulse Width
Oscillator
Switching Frequency
Switching Frequency
Switching Frequency
R
OSC
Voltage
Phase Difference
20
20
50
40
40
125
70
70
280
ns
ns
kΩ
COMP1,2 = 1.0 V, V
FB1(2)
= 0 to 1.2 V
V
FFB1(2)
= 0 V; Increase COMP1,2 until
GATE(H)1,2 starts switching
Duty cycle = 50%, Note 2
Note 2
−
0.30
40
−
150
0.45
70
−
300
0.60
100
300
ns
V
mV
ns
R
OSC
= 61.9 k; Measure GATE(H)1; Note 2
R
OSC
= 30.9 k; Measure GATE(H)1
R
OSC
= 15.1 k; Measure GATE(H)1; Note 2
R
OSC
= 30.9 k, Note 2
−
112
224
450
0.970
−
150
300
600
1.000
180
188
376
750
1.030
−
kHz
kHz
kHz
V
°
2. Guaranteed by design, not 100% tested in production.
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4
CS5422
ELECTRICAL CHARACTERISTICS (continued)
(0°C < T
A
< 70°C; 0°C < T
J
< 125°C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1
μF,
10.8 V < V
CC
< 13.2 V; 10.8 V < BST < 20 V, C
GATE(H)1,2
= C
GATE(L)1,2
= 1.0 nF, unless otherwise specified.)
Characteristic
Supply Currents
V
CC
Current
BST Current
Undervoltage Lockout
Start Threshold
Stop Threshold
Hysteresis
Hiccup Mode Overcurrent Protection
OVC Comparator Offset Voltage
Discharge Threshold
IS+ 1(2) Bias Current
IS− 1(2) Bias Current
OVC Common Mode Range
OVC Latch COMP1 Discharge Current
OVC Latch COMP2 Discharge Current
COMP1 Charge/Discharge
Ratio in OVC
COMP1 = 1.0 V
COMP2 = 1.0 V
−
0 V < IS+ 1(2) < 5.5 V
0 V < IS− 1(2) < 5.5 V
−
0 V < IS+ 1(2) < 5.5 V, 0 V < IS− 1(2) < 5.5 V
−
55
0.20
−1.0
−1.0
0
2.0
0.3
5.0
70
0.25
0.1
0.1
−
5.0
1.2
6.0
85
0.30
1.0
1.0
5.5
8.0
3.5
7.0
mV
V
μA
μA
V
μA
mA
−
GATE(H) Switching; COMP1,2 charging
GATE(H) not switching; COMP1,2 discharging
Start−Stop
7.8
7.0
0.5
8.6
7.8
0.8
9.4
8.6
1.5
V
V
V
COMP1,2 = 0 V (No Switching)
COMP1,2 = 0 V (No Switching)
−
−
13
3.5
17
6.0
mA
mA
Test Conditions
Min
Typ
Max
Unit
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