PIC32MZ1024EFH064T-I-MR datasheet, PDF

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PIC32MZ1024EFH064T-I-MR: Description32-bit Microcontrollers - MCU 32-BIT MCU 1024KB FL 512KB RAM, No Crypto; Categorysemiconductor The embedded processor and controller; File Size5MB，737 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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PIC32MZ1024EFH064T-I-MR Overview

32-bit Microcontrollers - MCU 32-BIT MCU 1024KB FL 512KB RAM, No Crypto

PIC32MZ1024EFH064T-I-MR Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Microchip
Product Category	32-bit Microcontrollers - MCU
RoHS	Details
Mounting Style	SMD/SMT
Package / Case	QFN-64
Core	MIPS32 M-Class
Data Bus Width	32 bit
Maximum Clock Frequency	200 MHz
Program Memory Size	1 MB
Data RAM Size	512 kB
ADC Resolution	12 bit
Number of I/Os	46 I/O
Operating Supply Voltage	2.1 V to 3.6 V
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Interface Type	CAN, Ethernet, I2C, JTAG, PMP, SPI, SQI, UART, USB
Packaging	Reel
Product	MCU
Program Memory Type	Flash
Data RAM Type	SRAM
Number of ADC Channels	24 Channel
Number of Timers/Counters	9 x 16 bit
Processor Series	PIC32MZEF
Factory Pack Quantity	3300
Supply Voltage - Max	3.6 V
Supply Voltage - Min	2.1 V
Watchdog Timers	Watchdog Timer
Unit Weight	0.007277 oz

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PIC32MZ Embedded Connectivity

with Floating Point Unit (EF) Family

32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with FPU,

Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog

Operating Conditions

• 2.1V to 3.6V, -40ºC to +85ºC, DC to 252 MHz

• 2.1V to 3.6V, -40ºC to +125ºC, DC to 180 MHz

Advanced Analog Features

• 12-bit ADC module:

- 18 Msps with up to six Sample and Hold (S&H) circuits

(five dedicated and one shared)

- Up to 48 analog inputs

- Can operate during Sleep and Idle modes

- Multiple trigger sources

- Six Digital Comparators and six Digital Filters

• Two comparators with 32 programmable voltage

references

• Temperature sensor with ±2ºC accuracy

Core: 252 MHz (up to 415 DMIPS) M-Class

16 KB I-Cache, 4 KB D-Cache

FPU for 32-bit and 64-bit floating point math

MMU for optimum embedded OS execution

microMIPS™ mode for up to 35% smaller code size

DSP-enhanced core:

- Four 64-bit accumulators

- Single-cycle MAC, saturating, and fractional math

- IEEE 754-compliant

• Code-efficient (C and Assembly) architecture

•

Communication Interfaces

• Two CAN modules (with dedicated DMA channels):

- 2.0B Active with DeviceNet™ addressing support

• Six UART modules (25 Mbps):

- Supports up to LIN 2.1 and IrDA

protocols

• Six 4-wire SPI modules (up to 50 MHz)

• SQI configurable as an additional SPI module (50 MHz)

• Five I

C modules (up to 1 Mbaud) with SMBus support

• Parallel Master Port (PMP)

• Peripheral Pin Select (PPS) to enable function remap

Clock Management

• Programmable PLLs and oscillator clock sources

• Fail-Safe Clock Monitor (FSCM)

• Independent Watchdog Timers (WDT) and Deadman

Timer (DMT)

• Fast wake-up and start-up

Power Management

• Low-power modes (Sleep and Idle)

• Integrated Power-on Reset (POR) and Brown-out Reset

(BOR)

Timers/Output Compare/Input Capture

•

Nine 16-bit or up to four 32-bit timers/counters

Nine Output Compare (OC) modules

Nine Input Capture (IC) modules

Real-Time Clock and Calendar (RTCC) module

Memory Interfaces

• 50 MHz External Bus Interface (EBI)

• 50 MHz Serial Quad Interface (SQI)

Input/Output

• 5V-tolerant pins with up to 32 mA source/sink

• Selectable open drain, pull-ups, pull-downs, and slew rate

controls

• External interrupts on all I/O pins

• PPS to enable function remap

Audio and Graphics Interfaces

•

Graphics interfaces: EBI or PMP

Audio data communication: I

S, LJ, and RJ

Audio control interfaces: SPI and I

Audio master clock: Fractional clock frequencies with USB

synchronization

Qualification and Class B Support

• AEC-Q100 REVH (Grade 1 -40ºC to +125ºC)

• Class B Safety Library, IEC 60730 (planned)

• Back-up internal oscillator

High-Speed (HS) Communication Interfaces



(with Dedicated DMA)

• USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller

• 10/100 Mbps Ethernet MAC with MII and RMII interface

Debugger Development Support

•

In-circuit and in-application programming

4-wire MIPS

Enhanced JTAG interface

Unlimited software and 12 complex breakpoints

IEEE 1149.2-compatible (JTAG) boundary scan

Non-intrusive hardware-based instruction trace

C/C++ compiler with native DSP/fractional and FPU support

MPLAB

Harmony Integrated Software Framework

TCP/IP, USB, Graphics, and mTouch™ middleware

MFi, Android™, and Bluetooth

audio frameworks

RTOS Kernels: Express Logic ThreadX, FreeRTOS™,

OPENRTOS

, Micriµm

µC/OS™, and SEGGER embOS

TFBGA

(1)

VTLA

LQFP

Security Features

• Crypto Engine with RNG for data encryption/decryption and

authentication (AES, 3DES, SHA, MD5, and HMAC)

• Advanced memory protection:

- Peripheral and memory region access control

Software and Tools Support

Direct Memory Access (DMA)

• Eight channels with automatic data size detection

• Programmable Cyclic Redundancy Check (CRC)

Packages

Type

QFN

TQFP

Pin Count

100

144

100

144

124

144

I/O Pins (up to)

120

Contact/Lead Pitch

0.50 mm

0.40 mm

0.50 mm

0.40 mm

0.65 mm

0.50 mm

Dimensions

9x9x0.9 mm 10x10x1 mm 12x12x1 mm 14x14x1 mm 16x16x1 mm 7x7x1.2 mm 7x7x1.2 mm 9x9x0.9 mm 20x20x1.40 mm

Note 1:

Contact your local Microchip Sales Office for information on the availability of devices in the 100-pin and 144-pin TFBGA packages



2015-2016 Microchip Technology Inc.

DS60001320D-page 1

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