Low Skew, 1-to-4, Crystal-to-LVCMOS/LVTTL
Fanout Buffer
83904I-02
Datasheet
General Description
The 83904I-02 is a low skew, high performance 1-to-4 Crystal-
to-LVCMOS Fanout Buffer. The 83904I-02 has selectable
single-ended clock or two crystal-oscillator inputs. There is an output
enable to disable the outputs by placing them into a high-impedance
state.
Guaranteed output and part-to-part skew characteristics make the
83904I-02 ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
Four LVCMOS / LVTTL outputs, 19
output impedance at
V
DD
= V
DDO
= 3.3V
Two crystal oscillator input pairs
LVCMOS / LVTTL clock input
Crystal input frequency range: 12MHz – 38.88MHz
Output frequency: 200MHz (maximum)
Output skew: 40ps (maximum) at V
DD
= V
DDO
= 3.3V
RMS phase jitter @ 25MHz output, using a 25MHz crystal,
(100Hz – 1MHz): 0.16ps (typical) at V
DD
= V
DDO
= 3.3V
RMS phase noise at 25MHz
Offset
Noise Power
100Hz .............. -118.4 dBc/Hz
1kHz................. -141.5 dBc/Hz
10kHz............... -157.2 dBc/Hz
100kHz............. -157.2 dBc/Hz
•
Power Supply Voltage Modes:
Core / Output
3.3V / 3.3V
3.3V / 2.5V
3.3V / 1.8V
2.5V / 2.5V
2.5V / 1.8V
Block Diagram
OE
CLK_SEL0
CLK_SEL1
Pullup
Pulldown
Pulldown
•
•
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Pin Assignment
XTAL_IN0
OSC
0 0
Q0
XTAL_OUT0
Q1
XTAL_IN1
CLK_SEL0
XTAL_OUT0
XTAL_IN0
V
DD
XTAL_IN1
XTAL_OUT1
CLK_SEL1
CLK
1
2
3
4
5
6
7
8
OSC
0 1
Q2
16
15
14
13
12
11
10
9
V
DDO
Q0
Q1
GND
Q2
Q3
V
DDO
OE
XTAL_OUT1
83904I-02
1 0
1 1
Q3
CLK
Pulldown
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc.
1
Revision B, April 8, 2016
83904I-02 Datasheet
Pin Descriptions and Pin Characteristics
Table 1. Pin Descriptions
Number
1,
7
2.
3
4
5,
6
8
9
10, 16
11, 12, 14, 15
13
Name
CLK_SEL0,
CLK_SEL1
XTAL_OUT0,
XTAL_IN0
V
DD
XTAL_IN1,
XTAL_OUT1
CLK
OE
V
DDO
Q3, Q2, Q1, Q0
GND
Input
Input
Power
Input
Input
Input
Power
Output
Power
Pulldown
Pullup
Type
Pulldown
Description
Clock select inputs. See Table 3,
Input Reference Function Table.
LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the
output.
Power supply pin.
Crystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the
output.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable pin. When LOW, outputs are in high-impedance state.
When HIGH, outputs are active. LVCMOS/LVTTL interface levels.
Output supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation
Capacitance
(per output)
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 2.0V
V
DDO
= 3.3V
R
OUT
Output Impedance
V
DDO
= 2.5V
V
DDO
= 1.8V
Test Conditions
Minimum
Typical
4
51
51
8
7
7
19
21
32
Maximum
Units
pF
k
k
pF
pF
pF
C
PD
Function Table
Table 3. Input Reference Function Table
Control Inputs
CLK_SEL1
0
0
1
1
CLK_SEL0
0
1
0
1
Reference
XTAL0 (default)
XTAL1
CLK
CLK
©2016 Integrated Device Technology, Inc.
2
Revision B, April 8, 2016
83904I-02 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
100.3C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
No Load & XTALx selected @ 12MHz
Power Supply Current
No Load & CLK selected
Output Supply Current
No Load & CLK selected
1
1
mA
mA
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
7
Units
V
V
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
No Load & XTALx selected @ 12MHz
Power Supply Current
No Load & CLK selected
Output Supply Current
No Load & CLK selected
1
1
mA
mA
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
7
Units
V
V
mA
Table 4C. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
No Load & XTALx selected @ 12MHz
Power Supply Current
No Load & CLK selected
Output Supply Current
No Load & CLK selected
1
1
mA
mA
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
7
Units
V
V
mA
©2016 Integrated Device Technology, Inc.
3
Revision B, April 8, 2016
83904I-02 Datasheet
Table 4D. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
No Load & XTALx selected @ 12MHz
Power Supply Current
No Load & CLK selected
Output Supply Current
No Load & CLK selected
1
1
mA
mA
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
3
Units
V
V
mA
Table 4E. Power Supply DC Characteristics,
V
DD
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
No Load & XTALx selected @ 12MHz
Power Supply Current
No Load & CLK selected
Output Supply Current
No Load & CLK selected
1
1
mA
mA
Test Conditions
Minimum
2.375
1.6
Typical
2.5
1.8
Maximum
2.625
2.0
3
Units
V
V
mA
Table 4F. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
Input Low Voltage
CLK,
CLK_SEL[0:1]
OE
CLK,
CLK_SEL[0:1]
OE
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
Input
High Current
V
DD
= V
IN
= 3.3V or 2.5V ± 5%
V
DD
= V
IN
= 3.3V or 2.5V ± 5%
V
DD
= 33.3V or 2.5V ± 5%,
V
IN
= 0V
V
DD
= 3.3V or 2.5V ± 5%,
V
IN
= 0V
V
DDO
= 3.3V ± 5%
V
OH
Output High Voltage; NOTE 1
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
V
DDO
= 3.3V ± 5%
V
OL
Output Low Voltage; NOTE 1
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
NOTE: Outputs terminated with 50 to V
DDO
/2. See Parameter Measurement section,
Load Test Circuit diagram.
-5
-150
2.6
1.8
1.2
0.6
0.5
0.4
Minimum
2.2
1.6
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.9
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
V
IL
I
IH
I
IL
Input
Low Current
©2016 Integrated Device Technology, Inc.
4
Revision B, April 8, 2016
83904I-02 Datasheet
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
12
Test Conditions
Minimum
Typical
Fundamental
38.88
50
7
1
MHz
pF
mW
Maximum
Units
AC Electrical Characteristics
Table 6A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Parameter
f
OUT
tp
LH
tsk(o)
tsk(pp)
tjit()
t
R
/ t
F
odc
t
EN
t
DIS
Symbol
Output
Frequency
w/external XTAL
w/external CLK
1.4
1.9
Test Conditions
Minimum
12
Typical
Maximum
38.88
200
2.4
40
700
25MHz, Integration Range:
100MHz – 1MHz
20% to 80%
<150MHz
100
45
46
0.16
800
55
54
10
10
Units
MHz
MHz
ns
ps
ps
ps
ps
%
%
ns
ns
Propagation Delay, Low to High;
NOTE 1
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
RMS Phase Jitter, Random; 4, 5
Output Rise/Fall Time
Output
Duty Cycle
w/external XTAL
w/external CLK
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc.
5
Revision B, April 8, 2016
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