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TP0606N3-G-P003

Description
MOSFET P-CH Enhancmnt Mode MOSFET
CategoryDiscrete semiconductor    The transistor   
File Size549KB,5 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
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TP0606N3-G-P003 Overview

MOSFET P-CH Enhancmnt Mode MOSFET

TP0606N3-G-P003 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
MakerMicrochip
Reach Compliance Codecompliant
Factory Lead Time6 weeks
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage60 V
Maximum drain current (ID)0.32 A
Maximum drain-source on-resistance3.5 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)35 pF
JEDEC-95 codeTO-92
JESD-30 codeO-PBCY-T3
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
Package shapeROUND
Package formCYLINDRICAL
Polarity/channel typeP-CHANNEL
surface mountNO
Terminal formTHROUGH-HOLE
Terminal locationBOTTOM
transistor applicationsSWITCHING
Transistor component materialsSILICON
Supertex inc.
P-Channel Enhancement-Mode
Vertical DMOS FET
Low threshold (-2.4V max.)
High input impedance
Low input capacitance (80pF typ.)
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
TP0606
Features
General Description
This low threshold, enhancement-mode (normally-off) transistor
utilizes a vertical DMOS structure and Supertex’s well-proven,
silicon-gate manufacturing process. This combination produces a
device with the power handling capabilities of bipolar transistors
and the high input impedance and positive temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
this device is free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Applications
Ordering Information
Device
TP0606
Package
TO-92
TP0606N3-G
NW
(Die in wafer form)
Wafer / Die Options
NJ
(Die on adhesive tape)
ND
(Die in waffle pack)
TP2506NW
TP2506NJ
TP2506ND
For packaged products, -G indicates package is RoHS compliant (‘Green’). Devices in Wafer / Die form are RoHS compliant (‘Green’).
Refer to Die Specification VF25 for layout and dimensions.
Product Summary
Device
TP0606N3-G
BV
DSS
/BV
DGS
(V)
R
DS(ON)
(max)
(Ω)
I
D(ON)
(min)
(A)
Pin Configuration
V
GS(th)
(max)
(V)
-60
3.5
-1.5
-2.4
SOURCE
DRAIN
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Value
BV
DSS
BV
DGS
±20V
-55
O
C to +150
O
C
GATE
TO-92 (N3)
Product Marking
S iT P
060 6
YYWW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
TO-92 (N3)
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Package may or may not include the following marks: Si or
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com

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Configuration SINGLE WITH BUILT-IN DIODE Single Single Single SINGLE WITH BUILT-IN DIODE Single Single Single
Product Category - MOSFET MOSFET MOSFET - MOSFET MOSFET MOSFET

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