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71016S15PHG8

Description
SRAM 64Kx16 ASYNCHRONOUS 5.0V STATIC RAM
Categorystorage   
File Size83KB,9 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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71016S15PHG8 Overview

SRAM 64Kx16 ASYNCHRONOUS 5.0V STATIC RAM

71016S15PHG8 Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIDT (Integrated Device Technology, Inc.)
Product CategorySRAM
RoHSDetails
Memory Size1 Mbit
Organization64 k x 16
Access Time15 ns
Interface TypeParallel
Supply Voltage - Max5.5 V
Supply Voltage - Min4.5 V
Supply Current - Max180 mA
Minimum Operating Temperature0 C
Maximum Operating Temperature+ 70 C
Mounting StyleSMD/SMT
Package / CaseTSOP-44
PackagingCut Tape
PackagingMouseReel
PackagingReel
Height1 mm
Length18.41 mm
Memory TypeSDR
TypeAsynchronous
Width10.16 mm
Moisture SensitiveYes
Factory Pack Quantity1500
CMOS Static RAM
1 Meg (64K x 16-Bit)
Features
Description
IDT71016S
64K x 16 advanced high-speed CMOS Static RAM
Equal access and cycle times
– Commercial : 12/15/20ns
– Industrial: 15/20ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly TTL-
compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Commercial and industrial product available in 44-pin
Plastic SOJ package and 44-pin TSOP package
The IDT71016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using high-perfomance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71016 has an output enable pin which operates as fast as 7ns,
with address access times as fast as 12ns. All bidirectional inputs and
outputs of the IDT71016 are TTL-compatible and operation is from a single
5V supply. Fully static asynchronous circuitry is used, requiring no clocks
or refresh for operation.
The IDT71016 is packaged in a JEDEC standard 44-pin Plastic SOJ
and 44-pin TSOP Type II.
Functional Block Diagram
OE
Output
Enable
Buffer
A0 - A15
Address
Buffers
Row / Column
Decoders
I/O 15
Chip
Enable
Buffer
Sense
Amps
and
Write
Drivers
8
Low
Byte
I/O
Buffer
8
8
High
Byte
I/O
Buffer
8
,
CS
I/O 8
WE
Write
Enable
Buffer
64K x 16
Memory
Array
16
I/O 7
I/O 0
BHE
Byte
Enable
Buffers
BLE
3210 drw 01
SEPTEMBER 2013
1
©2013 Integrated Device Technology, Inc.
DSC-3210/11
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