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DS4M125D-33

Description
Standard Clock Oscillators 3.3V Margining Clock w/LVPECL/LVDS Output
CategoryPassive components   
File Size137KB,7 Pages
ManufacturerMaxim
Websitehttps://www.maximintegrated.com/en.html
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DS4M125D-33 Overview

Standard Clock Oscillators 3.3V Margining Clock w/LVPECL/LVDS Output

DS4M125D-33 Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerMaxim
Product CategoryStandard Clock Oscillators
RoHSDetails
ProductStandard Clock Oscillators
Frequency125 MHz
Frequency Stability50 PPM
Operating Supply Voltage3.3 V
Supply Voltage - Min3.135 V
Supply Voltage - Max3.465 V
Output FormatLVDS
Termination StyleSMD/SMT
Package / CaseLCCC-10
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Length5 mm
Width3.2 mm
PackagingBulk
Current Rating100 mA
TypeClock Oscillator
Duty Cycle - Max55 %
Factory Pack Quantity30
Rev 0; 12/07
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
General Description
The DS4M125/DS4M133/DS4M200 are margining clock
oscillators with LVPECL or LVDS outputs. They are
designed to fit in a 5mm x 3.2mm ceramic package with
an AT-cut fundamental-mode crystal to form a complete
clock oscillator. The circuit can generate the following
frequencies and their ±5% frequency deviations:
125MHz, 133.33MHz, and 200MHz. The DS4M125/
DS4M133/DS4M200 employ a low-jitter PLL to generate
the frequencies. The typical phase jitter is less than
0.9ps RMS from 12kHz to 20MHz.
Frequency margining is a circuit operation to change
the output frequency to 5% higher or 5% lower than the
nominal frequency. Frequency margining is accom-
plished through the margining select pin, MS. This
three-state input pin accepts a three-level voltage signal
to control the output frequency. In a low-level state, the
output frequency is set to the nominal frequency. When
set to a high-level state, the frequency output is set to
the nominal frequency plus 5%. When set to the mid-
level state, the frequency output is equal to the nominal
frequency minus 5%. If left open, the MS pin is pulled
low by an internal 100kΩ (nominal) pulldown resistor.
The DS4M125/DS4M133/DS4M200 are available with
either an LVPECL or LVDS output. The output can be
disabled by pulling the OE pin low. When disabled,
both OUTP and OUTN levels of the LVPECL driver go to
the LVPECL bias voltage, while the output of the LVDS
driver is a logical one. The OE input is an active-high
logic signal and has an internal 100kΩ pullup resistor.
When OE is in a logic-high state, the OUTP and OUTN
outputs are enabled.
The devices operate from a single 3.3V supply voltage.
Frequency Margining: ±5%
Nominal Clock Output Frequencies: 125MHz,
133.33MHz, and 200MHz
Jitter < 0.9ps RMS from 12kHz to 20MHz
LVPECL or LVDS Output
3.3V Operating Voltage
Operating Temperature Range: -40°C to +85°C
Supply Current: < 100mA at 3.3V
Excellent Power-Supply Noise Rejection
5mm x 3.2mm Ceramic LCCC Package
Output Enable/Disable
Features
DS4M125/DS4M133/DS4M200
Ordering Information
PART
DS4M125P+33
DS4M125D+33
DS4M133P+33
DS4M133D+33
DS4M200P+33
DS4M200D+33
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
10 LCCC
10 LCCC
10 LCCC
10 LCCC
10 LCCC
10 LCCC
+Denotes
a lead(Pb)-free package. The lead finish is JESD97
category e4 (Au over Ni) and is compatible with both lead-based
and lead-free soldering processes.
Applications
Memory Clocks
RAID Systems
Pin Configuration and Selector Guide appear at end of
data sheet.
Typical Operating Circuit
VCC
0.1μF
0.01μF
OUTP
0.1μF
0.01μF
VCC
OUTP
50Ω
DS4M125/
MS
DS4M133/
OE
DS4M200
GND
OUTN
100Ω
DS4M125/
MS
DS4M133/
OE
DS4M200
GND
OUTN
PECL_BIAS AT
V
CC
- 2.0V
50Ω
LVDS OPTION
LVPECL OPTION
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

DS4M125D-33 Related Products

DS4M125D-33 DS4M200P+33 DS4M133P+33
Description Standard Clock Oscillators 3.3V Margining Clock w/LVPECL/LVDS Output Standard Clock Oscillators 3.3V Margining Clock w/LVPECL/LVDS Output Standard Clock Oscillators 3.3V Margining Clock w/LVPECL/LVDS Output
Is it lead-free? - Lead free Lead free
Is it Rohs certified? - conform to conform to
Maker - Maxim Maxim
Parts packaging code - LCC LCC
package instruction - HQCCN, HQCCN,
Contacts - 10 10
Reach Compliance Code - compliant compliant
ECCN code - EAR99 EAR99
JESD-30 code - R-CQCC-N10 R-CQCC-N10
length - 5 mm 5 mm
Number of terminals - 10 10
Maximum operating temperature - 85 °C 85 °C
Minimum operating temperature - -40 °C -40 °C
Maximum output clock frequency - 200 MHz 133.33 MHz
Package body material - CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code - HQCCN HQCCN
Package shape - RECTANGULAR RECTANGULAR
Package form - CHIP CARRIER, HEAT SINK/SLUG CHIP CARRIER, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius) - NOT SPECIFIED NOT SPECIFIED
Maximum seat height - 1.62 mm 1.62 mm
Maximum supply voltage - 3.465 V 3.465 V
Minimum supply voltage - 3.135 V 3.135 V
Nominal supply voltage - 3.3 V 3.3 V
surface mount - YES YES
technology - BIPOLAR BIPOLAR
Temperature level - INDUSTRIAL INDUSTRIAL
Terminal form - NO LEAD NO LEAD
Terminal pitch - 1 mm 1 mm
Terminal location - QUAD QUAD
Maximum time at peak reflow temperature - NOT SPECIFIED NOT SPECIFIED
width - 3.2 mm 3.2 mm
uPs/uCs/peripheral integrated circuit type - CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
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