Philips Semiconductors
Product data sheet
5-channel I
2
C hub
PCA9516A
DESCRIPTION
The PCA9516A is a CMOS integrated circuit intended for application
in I
2
C and SMBus systems.
While retaining all the operating modes and features of the I
2
C
system, it permits extension of the I
2
C-bus by buffering both the data
(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.
The I
2
C-bus capacitance limit of 400 pF restricts the number of
devices and bus length. Using the PCA9516A enables the system
designer to divide the bus into five segments off of a hub where any
segment to segment transition sees only one repeater delay.
It can also be used to run different buses at 5 V and 3.3 V or
400 kHz and 100 kHz buses where the 100 kHz bus is isolated
when 400 kHz operation of the other bus is required.
Two or more PCA9516As cannot be put in series.
The
PCA9516A design does not allow this configuration. Since there is
no direction pin, slightly different “legal” low voltage levels are used
to avoid lock-up conditions between the input and the output of each
repeater in the hub. A “regular LOW” applied at the input of a
PCA9516A will be propagated as a “buffered LOW” with a slightly
higher value on all the enabled outputs. When this “buffered LOW” is
applied to another PCA9515A, PCA9516A, or PCA9518 in series,
the second PCA9515A, PCA9516A, or PCA9518 will not recognize
it as a “regular LOW” and will not propagate it as a “buffered LOW”
again. The PCA9510/9511/9513/9514 and PCA9512 cannot be used
in series with the PCA9515A, PCA9516A, or PCA9518 but can be
used in series with themselves since they use shifting instead of
static offsets to avoid lock-up conditions.
FEATURES
•
5 channel, bi-directional buffer
•
I
2
C-bus and SMBus compatible
•
Active HIGH individual repeater enable input
•
Open-drain input/outputs
•
Lock-up free operation
•
Supports arbitration and clock stretching across the repeater
•
Accommodates standard mode and fast mode I
2
C devices and
•
Powered-off high impedance I
2
C pins
•
Operating supply voltage range of 2.3 V to 3.6 V
•
5.5 V tolerant I
2
C and enable pins
•
0 kHz to 400 kHz clock frequency
1
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
•
Latch-up testing is done to JEDEC Standard JESD78 which
•
Package offerings: SO16 and TSSOP16
exceeds 100 mA.
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101.
multiple masters
ORDERING INFORMATION
DESCRIPTION
16-pin plastic SO
16-pin plastic TSSOP
TEMPERATURE RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
ORDER CODE
PCA9516AD
PCA9516APW
TOPSIDE MARK
PCA9516AD
PA9516A
DRAWING NUMBER
SOT109-1
SOT403-1
Standard packing quantities and other packaging data is available at www.standardproducts.philips.com/packaging.
1.
The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
2004 Sep 29
2
Philips Semiconductors
Product data sheet
5-channel I
2
C hub
PCA9516A
FUNCTIONAL DESCRIPTION
The PCA9516A is a five way hub repeater, which enables
and
similar bus systems to be expanded with only one repeater delay
and no functional degradation of system performance.
The PCA9516A contains five bi-directional, open drain buffers
specifically designed to support the standard low-level-contention
arbitration of the I
2
C-bus. Except during arbitration or clock
stretching, the PCA9516A acts like five pairs of non-inverting, open
drain buffers, one for SDA and one for SCL.
I
2
C
SDA0/SCL0. If the SDA0/SCL0 port is not used, the pins need to be
pulled to V
CC
through appropriately sized resistors.
The PCA9516A is 5.5 V tolerant so it does not require any additional
circuitry to translate between the different bus voltages.
When one side of the PCA9516A is pulled LOW by a device on the
I
2
C-bus, a CMOS hysteresis type input detects the falling edge and
causes an internal driver on the other side to turn on, thus causing
the other side to also go LOW. The side driven LOW by the
PCA9516A will typically be at V
OL
= 0.5 V.
Enable
The enable pins EN1 through EN4 are active HIGH and have
internal pull-up resistors. Each enable pin ENn controls its
associated SDAn and SCLn ports. When LOW, the ENn pin blocks
the inputs from SDAn and SCLn as well as disabling the output
drivers on the SDAn and SCLn pins. The enable pins should only
change state when both the global bus and the local port are in an
idle state to prevent system failures.
The active HIGH enable pins allow the use of open drain drivers
which can be wire-ORed to create a distributed enable where either
centralized control signal (master) or spoke signal (submaster) can
enable the channel when it is idle.
3.3 V
5V
SDA
SCL
BUS
MASTER
SDA0
SCL0
SDA1
SCL1
3.3 V
SDA
SLAVE 1
SCL
400 kHz
EN1
EN2
EN3
EN4
400 kHz
SDA2
SCL2
5V
PCA9516A
SDA
SLAVE 2
SCL
400 kHz
I
2
C Systems
As with the standard I
2
C system, pull-up resistors are required to
provide the logic HIGH levels on the Buffered bus. (Standard
open-collector configuration of the I
2
C-bus). The size of these
pull-up resistors depends on the system, but each side of the
repeater must have a pull-up resistor. This part is designed to work
with standard mode and fast mode I
2
C devices in addition to SMBus
devices. Standard mode I
2
C devices only specify 3 mA output drive,
this limits the termination current to 3 mA in a generic I
2
C system
where standard mode devices and multiple masters are possible.
Please see Application Note AN255
“I
2
C & SMBus Repeaters, Hubs
and Expanders”
for additional information on sizing resistors and
precautions when using more than one PCA9515A/PCA9516A in a
system or using the PCA9515A/16A in conjunction with the P82B96.
SDA3
SCL3
SDA
SLAVE 3
SCL
100 kHz
3.3 V or 5 V
APPLICATION INFORMATION
A typical application is shown in Figure 4. In this example, the
system master is running on a 3.3 V I
2
C-bus while the slave is
connected to a 5 V bus. All buses run at 100 kHz unless slave 3 is
isolated and then the master bus and slave 1 and 2 can run at
400 kHz.
Any segment of the hub can talk to any other segment of the hub.
Bus masters and slaves can be located on all five segments with
400 pF load allowed on each segment.
Unused ports should be isolated by holding the enable pin to GND
and/or pulling SDA/SCL pins to V
CC
through appropriately sized
resistors. The primary bus master is normally connected to
SDA4
SCL4
SW02249
Figure 4. Typical application
2004 Sep 29
5
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