PCA9519
4-channel level translating I
2
C-bus/SMBus repeater
Rev. 01 — 22 June 2006
Objective data sheet
1. General description
The PCA9519 is a 4-channel level translating I
2
C-bus/SMBus repeater that enables the
processor low voltage 2-wire serial bus to interface with standard I
2
C-bus or SMBus I/O.
While retaining all the operating modes and features of the I
2
C-bus system during the
level shifts, it also permits extension of the I
2
C-bus by providing bidirectional buffering for
both the data (SDA) and the clock (SCL) lines, thus enabling the I
2
C-bus or SMBus
maximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins are
over-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
The port B drivers are compliant with SMBus I/O levels, while port A uses a current
sensing mechanism to detect the input or output LOW signal which prevents bus lock-up.
The port A uses a 1 mA current source for pull-up and a 200
Ω
pull-down driver. This
results in a LOW on port A accommodating smaller voltage swings. The output pull-down
on the port A internal buffer LOW is set for approximately 0.2 V, while the input threshold
of the internal buffer is set about 50 mV lower than that of the output voltage LOW. When
the port A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on the port B
drives a hard LOW and the input level is set at 0.3 of SMBus or I
2
C-bus voltage level
which enables port B to connect to any other I
2
C-bus device or buffer.
The PCA9519 drivers are not enabled unless V
CC(A)
is above 0.8 V and V
CC(B)
is above
2.5 V. The enable (EN) pin can also be used to turn the drivers on and off under system
control. Caution should be observed to only change the state of the EN pin when the bus
is idle.
2. Features
I
4-channel (4 SCL/SDA pairs), bidirectional buffer isolates capacitance and allows
400 pF on port B of the device
I
Voltage level translation from port A (1 V to V
CC(B)
−
1 V) to port B (3.0 V to 5.5 V)
I
Requires no external pull-up resistors on lower voltage port A
I
Active HIGH repeater enable input
I
Open-drain inputs/outputs
I
Lock-up free operation
I
Supports arbitration and clock stretching across the repeater
I
Accommodates Standard-mode and Fast-mode I
2
C-bus devices and multiple masters
I
Powered-off high-impedance I
2
C-bus pins
I
Operating supply voltage range of 1.0 V to V
CC(B)
−
1 V on port A, 3.0 V to 5.5 V on
port B
I
5 V tolerant B-side SCL and SDA and enable pins
Philips Semiconductors
PCA9519
4-channel level translating I
2
C-bus/SMBus repeater
I
0 Hz to 400 kHz clock frequency
Remark:
The maximum system operating frequency may be less than 400 kHz
because of the delays added by the repeater.
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: TSSOP20, HVQFN24
3. Ordering information
Table 1.
Ordering information
Package
Name
TSSOP20
HVQFN24
Description
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4
×
4
×
0.85 mm
Version
SOT616-1
plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
Type number Topside
mark
PCA9519PW
PCA9519BS
PCA9519
9519
4. Functional diagram
V
CC(A)
V
CC(B)
PCA9519
V
CC(A)
1 mA
A1
V
CC(A)
1 mA
B1
A2
B2
V
CC(A)
1 mA
A8
B8
EN
002aab643
GND
Fig 1. Functional diagram of PCA9519
PCA9519_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 22 June 2006
2 of 17
Philips Semiconductors
PCA9519
4-channel level translating I
2
C-bus/SMBus repeater
5. Pinning information
5.1 Pinning
23 V
CC(A)
22 GND
21 n.c.
24 A1
EN
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
20 V
CC(B)
19 A1
18 A2
17 A3
16 A4
15 A5
14 A6
13 A7
12 A8
11 V
CC(A)
002aab640
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
V
CC(B)
10
EN 11
B8 12
7
8
9
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
002aab641
terminal 1
index area
PCA9519BS
PCA9519PW
n.c.
GND 10
Transparent top view
Fig 2. Pin configuration for TSSOP20
Fig 3. Pin configuration for HVQFN24
5.2 Pin description
Table 2.
Symbol
EN
GND
V
CC(A)
A1
A2
A3
A4
A5
A6
A7
A8
V
CC(B)
B8
B7
B6
B5
B4
B3
Pin description
Pin
TSSOP20
1
10
11
19
18
17
16
15
14
13
12
20
9
8
7
6
5
4
HVQFN24
11
22
[1]
23
24
1
2
3
4
5
6
7
10
12
13
14
15
16
17
enable input (active HIGH)
ground (0 V)
port A power supply
A1 port (low voltage side)
[2]
A2 port (low voltage side)
[2]
A3 port (low voltage side)
[2]
A4 port (low voltage side)
[2]
A5 port (low voltage side)
[2]
A6 port (low voltage side)
[2]
A7 port (low voltage side)
[2]
A8 port (low voltage side)
[2]
port B power supply
B8 port (SMBus/I
2
C-bus side)
[2]
B7 port (SMBus/I
2
C-bus side)
[2]
B6 port (SMBus/I
2
C-bus side)
[2]
B5 port (SMBus/I
2
C-bus side)
[2]
B4 port (SMBus/I
2
C-bus side)
[2]
B3 port (SMBus/I
2
C-bus side)
[2]
Description
PCA9519_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 22 June 2006
n.c.
A8
20 n.c.
3 of 17
Philips Semiconductors
PCA9519
4-channel level translating I
2
C-bus/SMBus repeater
Pin description
…continued
Pin
TSSOP20
HVQFN24
18
19
8, 9, 20, 21
B2 port (SMBus/I
2
C-bus side)
[2]
B1 port (SMBus/I
2
C-bus side)
[2]
not connected
3
2
-
Description
Table 2.
Symbol
B2
B1
n.c.
[1]
HVQFN package die supply ground is connected to both the GND pin and the exposed center pad. The
GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
Port A and port B can be used for either SCL or SDA.
[2]
6. Functional description
Refer to
Figure 1 “Functional diagram of PCA9519”.
The PCA9519 enables I
2
C-bus or SMBus translation down to V
CC(A)
as low as 1.0 V
without degradation of system performance. The PCA9519 contains 8 bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage and 3.3 V SMBus or 5 V I
2
C-bus. Port B I/Os are over-voltage
tolerant to 5.5 V even when the device is unpowered.
The PCA9519 includes a power-up circuit that keeps the output drivers turned off until
V
CC(B)
is above 2.5 V and the V
CC(A)
is above 0.8 V. V
CC(B)
and V
CC(A)
can be applied in
any sequence at power-up. After power-up and with the EN pin HIGH, a LOW level on the
port A (below approximately 0.15 V) turns the corresponding port B driver (either SDA or
SCL) on and drives the port B down to about 0 V. When port A rises above approximately
0.15 V, the port B pull-down driver is turned off and the external pull-up resistor pulls the
pin HIGH. When the port B falls first and goes below 0.3V
CC(B)
, the port A driver is turned
on and the port A pulls down to 0.2 V (typical). The port B pull-down is not enabled unless
the port A voltage goes below V
ILc
. If the port A low voltage goes below V
ILc
, the port B
pull-down driver is enabled until the port A rises above approximately 0.15 V (V
ILc
), then
the port B, if not externally driven LOW, will continue to rise being pulled up by the
external pull-up resistor.
Remark:
Ground offset between the PCA9519 ground and the ground of devices on
port A of the PCA9519 must be avoided.
The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of
sinking 3 mA of current at 0.4 V will have an output resistance of 133
Ω
or less (R = E / I).
Such a driver will share enough current with the port A output pull-down of the PCA9519
to be seen as a LOW as long as the ground offset is zero. If the ground offset is greater
than 0 V, then the driver resistance must be less. Since V
ILc
can be as low as 90 mV at
cold temperatures and the low end of the current distribution, the maximum ground offset
should not exceed 50 mV.
Bus repeaters that use an output offset are not interoperable with port A of the PCA9519
as their output LOW levels will not be recognized by the PCA9519 as a LOW. If the
PCA9519 is placed in an application where the V
IL
of the port A of the PCA9519 does not
PCA9519_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 22 June 2006
4 of 17
Philips Semiconductors
PCA9519
4-channel level translating I
2
C-bus/SMBus repeater
go below its V
ILc
it will pull the port B LOW initially when the port A input transitions LOW
but port B will return HIGH, so it will not reproduce the port A input on port B. Such
applications should be avoided.
Port B is interoperable with all I
2
C-bus slaves, masters, and repeaters.
6.1 Enable
The EN pin is active HIGH and allows the user to select when the repeater is active. This
can be used to isolate a badly behaved slave on power-up until after the system power-up
reset. It should never change state during an I
2
C-bus operation because disabling during
a bus operation will hang the bus and enabling part way through a bus cycle could
confuse the I
2
C-bus parts being enabled.
The enable pin should only change state when the bus and the repeater port are in an idle
state to prevent system failures.
6.2 I
2
C-bus systems
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I
2
C-bus).
The size of these pull-up resistors depends on the system. Each of the port A I/Os has an
internal pull-up current source and does not require the external pull-up resistor. The
port B is designed to work with Standard mode and Fast mode I
2
C-bus devices in addition
to SMBus devices. Standard mode I
2
C-bus devices only specify 3 mA output drive; this
limits the termination current to 3 mA in a generic I
2
C-bus system where Standard mode
devices and multiple masters are possible. Under certain conditions higher termination
currents can be used.
7. Application design-in information
A typical application is shown in
Figure 4.
In this example, the CPU is running on a 1.1 V
I
2
C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
1.1 V
3.3 V
10 kΩ
10 kΩ
V
CC(A)
SDA
SCL
1.1 V
CPU
10 kΩ
V
CC(B)
B1
B2
SDA
SCL
MASTER
400 kHz
A1
A2
PCA9519
A8
EN
B8
bus A
bus B
002aab642
Fig 4. Typical application
PCA9519_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 22 June 2006
5 of 17
Embedded System
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