DS2064
DS2064
8K x 8 Static RAM
FEATURES
PIN ASSIGNMENT
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE2
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
•
Low power CMOS design
•
Standby current
50 nA max at
100 nA max at
1
µA
max at
t
A
= 25°C V
CC
= 3.0V
t
A
= 25°C V
CC
= 5.5V
t
A
= 60°C V
CC
= 5.5V
•
Full operation for V
CC
= 4.5V to 5.5V
•
Data Retention Voltage = 5.5V to 2.0V
•
Access time equals 200 ns at 5.0V
•
Operating temperature range of –40°C to +85°C
•
Full static operation
•
TTL compatible inputs and outputs
•
Available in 28–pin DIP and 28–pin SOIC packages
•
Suitable for both battery operated and battery backup
applications
DS2064–200 28–PIN DIP (600 MIL)
DS2064S–200 28–PIN SOIC (330 MIL)
PIN DESCRIPTION
A0–A12
DQ0–DQ7
CE1, CE2
WE
OE
V
CC
GND
NC
–
–
–
–
–
–
–
–
Address Inputs
Data Input/Output
Chip Enable Inputs
Write Enable Input
Output Enable Input
5V Power Supply Input
Ground
No Connection
DESCRIPTION
The DS2064 is a 65536–bit low power, fully static ran-
dom access memory organized as 8192 words by eight
bits using CMOS technology. The device operates from
a single power supply with a voltage input between 4.5V
and 5.5V. The chip enable inputs (CE1 and CE2) are
used for device selection and can be used in order to
achieve the minimum standby current mode, which fa-
cilitates both battery operate and battery backup appli-
cations. The device provides fast access time of 200 ns
and is most suitable for low power applications where
battery operation or battery backup for nonvolatility are
required. The DS2064 is a JEDEC–standard 8K x 8
SRAM and is pin–compatible with ROM and EPROM of
similar density.
022598 1/9
DS2064
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
V
IN
, V
I/O
T
STG
T
OPR
T
SOLDER
PARAMETER
Power Supply Voltage
Input, Input/Output Voltage
Storage Temperature
Operating Temperature
Soldering Temperature/Time
RATING
–0.3V to +7.0V
–0.3 to V
CC
+ 0.3V
–55°C to +125°C
–40°C to +85°C
260°C for 10 seconds
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Voltage
SYMBOL
V
CC
V
IH
V
IL
V
DR
MIN
4.5
2.0
–0.3
2.0
TYP
5.0
MAX
5.5
V
CC
+ 0.3
0.8
5.5
(t
A
= –40
°
C to +85
°
C)
UNITS
V
V
V
V
NOTES
DC CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
Output High Current
Output Low Current
Standby Current
Standby Current
Standby Current
Operating Current
SYMBOL
I
IL
I
LO
I
OH
I
OL
I
CCS1
I
CCS2
I
CCS2
I
CCO
CONDITIONS
0V < V
IN
< V
CC
CE1=V
IH,
0V<V
IO
<V
CC
V
OH
= 2.4V
V
OL
= 0.4V
CE1 = 2.0V
CE1>V
CC
–0.5V t
A
=60°C
CE1>V
CC
–0.5V t
A
=25°C
CE1=0.8V, 200 ns cycle
(t
A
= –40
°
C to +85
°
C; V
CC
=5V
±
10%)
MIN
TYP
MAX
+0.1
+0.5
–1.0
4.0
0.5
1
100
70
UNITS
µA
µA
mA
mA
mA
µA
nA
mA
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN
TYP
5
5
MAX
10
12
UNITS
pF
pF
(t
A
= 25°C)
NOTES
022598 2/9
DS2064
AC CHARACTERISTICS, READ CYCLE
PARAMETER
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
CE or OE to Output Active
Output to High–Z from
Deselection
Output Hold from Address
Change
SYMBOL
t
RC
t
ACC
t
OE
t
CO
t
COE
t
OD
t
OH
5
10
5
MIN
200
(t
A
= –40
°
C to +85
°
C; V
CC
=5V
±
10%)
TYP
MAX
UNITS
ns
200
100
200
ns
ns
ns
ns
60
ns
ns
NOTES
AC CHARACTERISTICS, WRITE CYCLE
PARAMETER
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High–Z from WE
Output Active from WE
Data Setup Time
Data Hold Time
SYMBOL
t
WC
t
WP
t
AW
t
WR
t
ODW
t
OEW
t
DS
t
DH
5
80
0
MIN
200
150
0
10
(t
A
= –40
°
C to +85
°
C; V
CC
=5V
±
10%)
TYP
MAX
UNITS
ns
ns
ns
ns
70
ns
ns
ns
ns
7
7
NOTES
TIMING DIAGRAM: READ CYCLE
t
RC
ADDRESSES
V
IH
V
IL
V
IH
V
IL
t
OH
V
IH
CE
V
IL
V
IH
OE
V
IL
t
COE
t
COE
D
OUT
SEE NOTE 1
t
OD
V
OH
OUTPUT
V
OH
V
OL
DATA VALID V
OL
t
ACC
V
IH
t
CO
t
OD
t
OE
V
IH
V
IH
V
IL
022598 3/9
DS2064
TIMING DIAGRAM: WRITE CYCLE 1
t
WC
ADDRESSES
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AW
CE
V
IL
V
IL
t
WP
WE
V
IH
V
IL
V
IL
V
IH
t
WR
t
OEW
t
ODW
D
OUT
t
DS
V
IH
D
IN
V
IL
SEE NOTES 2, 3, 4, 5, 6 AND 7
t
DH
V
IH
DATA IN STABLE
V
IL
022598 4/9
DS2064
TIMING DIAGRAM: WRITE CYCLE 2
t
WC
V
IH
ADDRESSES
V
IL
t
AW
CE
V
IH
V
IL
V
IL
V
IH
t
WP
V
IH
V
IL
t
WR
V
IH
V
IL
V
IH
WE
V
IL
V
IL
t
COE
t
ODW
D
OUT
t
DS
V
IH
D
IN
V
IL
SEE NOTES 2, 3, 4, 5, 6 AND 7
t
DH
V
IH
DATA IN STABLE
V
IL
TIMING DIAGRAM: DATA RETENTION – POWER UP, POWER DOWN
V
CC
DATA RETENTION MODE
2.7V
V
IH
t
CDR
t
R
V
CC
- 0.2V
V
IL
CE
GND
SEE NOTE 8
022598 5/9
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
