DZPD6710VCB datasheet, PDF - EEWORLD Datasheet

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DZPD6710VCB: DescriptionISA-to-PC-Card (PCMCIA) Controllers; CategoryThe embedded processor and controller Microcontrollers and processors; File Size718KB，138 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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DZPD6710VCB Overview

ISA-to-PC-Card (PCMCIA) Controllers

DZPD6710VCB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	LQFP-144
Contacts	144
Reach Compliance Code	compli
Other features	ALSO REQUIRES 5V SUPPLY
Address bus width	24
Bus compatibility	ISA
maximum clock frequency	25 MHz
External data bus width	16
JESD-30 code	S-PQFP-G144
JESD-609 code	e0
length	20 mm
Number of terminals	144
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP144,.87SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3,5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	20 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	20 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCMCIA
Base Number Matches	1

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PD6710/’22

ISA-to-PC-Card (PCMCIA) Controllers

Datasheet

The PD6710 and PD6722 are single-chip PC Card (PCMCIA) controller solutions capable of

controlling one (PD6710) or two (PD6722) PC Card sockets. The chips are compliant with PC

Card Standard, PCMCIA 2.1, and JEIDA 4.1 and are optimized for use in embedded

applications and notebook/handheld/mobile computer systems where reduced form factor and

low power consumption are critical design objectives. With the PD6710, a complete PC Card

solution with power-control logic can occupy less than 1.5 square inches (excluding the socket

connector). With the PD6722, a complete dual-socket PC Card solution with power-control

logic can occupy less than 2 square inches (excluding socket connectors).

The chips employ energy-efficient mixed-voltage technology that can reduce system power

consumption by over 50 percent. The chips also provide: a Low-Power Dynamic mode, which

automatically stops the internal clock during periods of card inactivity; a software-controlled

Suspend mode, which dramatically reduces power by disabling most of the internal circuitry and

stopping data transactions to the PC Cards; and a hardware-controlled Super Suspend mode,

which reduces current to the

A range.

Personal computer applications typically access PC Cards through a third-party socket/card-

services software interface. To assure full compatibility with industry-standard socket/card-

services software and PC Card applications, the register set in the PD6710 and PD6722 is a

superset of the Intel



82365SL register set.

The chips provide fully buffered PC Card interfaces, meaning that no external logic is required

for buffering signals to/from the interface, and power consumption can be controlled by limiting

signal transitions on the PC Card bus.

As of May 2001, this document replaces the Basis Communications

Corp. document

CL-PD6710/’22 — ISA-to-PC-Card Host Adapters.

May 2001

ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22

Contents

1.0

2.0

3.0

Product Features

........................................................................................................9

General Conventions

..............................................................................................11

2.1

3.1

3.2

3.3

3.4

Numbers and Units..............................................................................................11

Pin Diagrams.......................................................................................................13

Pin Description Conventions ...............................................................................14

Pin Descriptions ..................................................................................................16

Power-On Configuration Summary .....................................................................25

System Architecture ............................................................................................27

4.1.1 PC Card Basics ......................................................................................27

4.1.2 PD67XX Windowing Capabilities ...........................................................27

4.1.3 PD67XX Functional Blocks ....................................................................30

4.1.4 Interrupts ................................................................................................30

4.1.5 Alternate Functions of Interrupt Pins ......................................................31

4.1.6 General-Purpose Strobe Feature ...........................................................32

4.1.7 Voltage Sense Pins ................................................................................32

4.1.8 PD67XX Power Management ................................................................32

4.1.9 Socket Power Management Features ....................................................34

4.1.10 Write FIFO..............................................................................................35

4.1.11 Bus Sizing ..............................................................................................35

4.1.12 Programmable PC Card Timing .............................................................36

4.1.13 DMA Mode Operation for the PD6722 ...................................................36

4.1.14 Selective Data Drive for I/O Windows ....................................................36

Host Access to Registers ....................................................................................36

Power-On Setup..................................................................................................38

Pin Information

..........................................................................................................12

4.0

Introduction

................................................................................................................27

4.1

4.2

4.3

5.0

6.0

....................................................................39

Operation Registers

................................................................................................41

6.1

6.2

Index....................................................................................................................41

Data.....................................................................................................................44

Chip Revision ......................................................................................................46

Interface Status ...................................................................................................47

Power Control......................................................................................................48

Interrupt and General Control..............................................................................51

Card Status Change............................................................................................52

Management Interrupt Configuration...................................................................54

Mapping Enable ..................................................................................................55

I/O Window Control .............................................................................................58

System I/O Map 0–1 Start Address Low .............................................................59

7.0

Chip Control Registers

..........................................................................................46

7.1

7.2

7.3

7.4

7.5

7.6

7.7

8.0

I/O Window Mapping Registers

..........................................................................58

8.1

8.2

Datasheet

PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers

8.3

8.4

8.5

8.6

8.7

System I/O Map 0–1 Start Address High ............................................................ 60

System I/O Map 0–1 End Address Low .............................................................. 60

System I/O Map 0–1 End Address High ............................................................. 61

Card I/O Map 0–1 Offset Address Low ............................................................... 62

Card I/O Map 0–1 Offset Address High .............................................................. 62

System Memory Map 0–4 Start Address Low..................................................... 64

System Memory Map 0–4 Start Address High .................................................... 65

System Memory Map 0–4 End Address Low ...................................................... 66

System Memory Map 0–4 End Address High ..................................................... 66

Card Memory Map 0–4 Offset Address Low ....................................................... 67

Card Memory Map 0–4 Offset Address High ...................................................... 68

Misc Control 1 ..................................................................................................... 70

FIFO Control ....................................................................................................... 72

Misc Control 2 ..................................................................................................... 72

Chip Information.................................................................................................. 74

ATA Control......................................................................................................... 75

Extended Index ................................................................................................... 77

Extended Data .................................................................................................... 77

10.7.1 Data Mask 0–1 ....................................................................................... 78

10.7.2 Extension Control 1 (PD6722 only, formerly DMA Control) ................... 78

10.7.3 Maximum DMA Acknowledge Delay (PD6722 only) .............................. 79

10.7.4 External Data (PD6722 only, Socket A, Index 2Fh) ............................... 81

10.7.5 External Data (PD6722 only, Socket A, Index 6Fh) ............................... 82

10.7.6 Extension Control 2 (PD6722 only) ........................................................ 83

Setup Timing 0–1 ............................................................................................... 84

Command Timing 0–1......................................................................................... 85

Recovery Timing 0–1 .......................................................................................... 86

9.0

Memory Window Mapping Registers

............................................................... 64

9.1

9.2

9.3

9.4

9.5

9.6

10.0

Extension Registers

................................................................................................ 70

10.1

10.2

10.3

10.4

10.5

10.6

10.7

11.0

Timing Registers

...................................................................................................... 84

11.1

11.2

11.3

12.0

13.0

ATA Mode Operation

.............................................................................................. 88

Using GPSTB Pins for External Port Control

(PD6722 only)

13.1

13.2

13.3

Control of GPSTB Pins ....................................................................................... 91

Example Implementations of GPSTB-Controlled Read and Write Ports............. 93

GPSTB in Suspend Mode ................................................................................... 94

14.0

15.0

VS1# and VS2# Voltage Detection

.................................................................... 95

DMA Operation (PD6722 only)

............................................................................ 97

15.1

15.2

15.3

15.4

DMA Capabilities of the PD6722......................................................................... 97

DMA-Type PC Card Cycles ................................................................................ 97

ISA Bus DMA Handshake Signal ........................................................................ 98

Configuring the PD6722 Registers for a DMA Transfer ...................................... 98

15.4.1 Programming the DMA Request Pin from the Card ............................... 98

15.4.2 Configuring the Socket Interface for I/O ................................................. 99

Datasheet

ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22

15.4.3

15.4.4

15.4.5

15.4.6

Preventing Dual Interpretation of DMA Handshake Signals...................99

Turning On DMA System .....................................................................100

The DMA Transfer Process ..................................................................100

Terminal Count to Card at Conclusion of Transfer ..............................100

16.0

Electrical Specifications

......................................................................................101

16.1

16.2

16.3

16.4

Absolute Maximum Ratings...............................................................................101

DC Specifications ..............................................................................................101

AC Timing Specifications ..................................................................................104

ISA Bus Timing..................................................................................................104

16.4.1 Reset Timing ........................................................................................107

16.4.2 System Interrupt Timing .......................................................................107

16.4.3 General-Purpose Strobe Timing (PD6722 only)...................................108

16.4.4 Input Clock Specification ......................................................................108

16.4.5 PC Card Bus Timing Calculations ........................................................109

144-Pin LQFP Package.....................................................................................121

208-Pin MQFP Package....................................................................................122

208-Pin LQFP Package.....................................................................................123

17.0

Package Specifications

.......................................................................................121

17.1

17.2

17.3

18.0

19.0

Order Numbers Example

.....................................................................................124

Appendix A

...............................................................................................................125

19.1

19.2

19.3

19.4

19.5

19.6

19.1.1 Operation Registers .............................................................................125

Chip Control Registers ......................................................................................125

I/O Window Mapping Registers.........................................................................127

Memory Window Mapping Registers.................................................................129

Extension Registers ..........................................................................................130

Timing Registers ..............................................................................................133

Index

.......................................................................................................................................135

Datasheet

DZPD6710VCB Related Products

	DZPD6710VCB	DZPD6722VCCE	PD6710	SPD6722QCCE
Description	ISA-to-PC-Card (PCMCIA) Controllers	ISA-to-PC-Card (PCMCIA) Controllers	ISA-to-PC-Card (PCMCIA) Controllers	ISA-to-PC-Card (PCMCIA) Controllers
Is it Rohs certified?	incompatible	incompatible	-	incompatible
Parts packaging code	QFP	QFP	-	QFP
package instruction	LQFP-144	LFQFP, QFP208,1.2SQ,20	-	FQFP, QFP208,1.2SQ,20
Contacts	144	208	-	208
Reach Compliance Code	compli	unknow	-	unknow
Base Number Matches	1	1	-	1

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