PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
Rev. 02 — 8 June 2006
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
I
Logic level compatible
I
Low gate charge
1.3 Applications
I
DC-to-DC converters
I
Switched-mode power supplies
1.4 Quick reference data
I
V
DS
≤
30 V
I
R
DSon
≤
17 mΩ
I
I
D
≤
43.4 A
I
P
tot
≤
57.6 W
2. Pinning information
Table 1.
Pin
1
2
3
mb
Pinning
Description
gate (G)
drain (D)
source (S)
mounting base;
connected to drain
G
[1]
Simplified outline
mb
mb
Symbol
D
2
1
3
1 2 3
mbb076
S
SOT428 (DPAK)
[1]
SOT78 (3-lead TO-220AB)
It is not possible to make a connection to pin 2 of the SOT428 package.
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2.
Ordering information
Package
Name
PHD36N03LT
PHP36N03LT
DPAK
SC-46
Description
plastic single-ended surface-mounted package; 3 leads (one lead
cropped)
plastic single-ended package; heatsink mounted; 1 mounting hole;
3-lead TO-220AB
Version
SOT428
SOT78
Type number
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage
drain-gate voltage (DC)
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
T
mb
= 25
°C;
V
GS
= 10 V; see
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 10 V; see
Figure 2
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
see
Figure 3
T
mb
= 25
°C;
see
Figure 1
Conditions
25
°C ≤
T
j
≤
175
°C
25
°C ≤
T
j
≤
175
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−55
−55
-
-
Max
30
30
±20
43.4
30.7
173.6
57.6
+175
+175
43.4
173.6
Unit
V
V
V
A
A
A
W
°C
°C
A
A
Source-drain diode
PHD_PHP36N03LT_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 8 June 2006
2 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
120
P
der
(%)
80
03aa16
120
I
der
(%)
80
03aa24
40
40
0
0
50
100
150
T
mb
(
°
C)
200
0
0
50
100
150
200
T
mb
(°C)
P
tot
P
der
=
-----------------------
×
100
%
-
P
tot
(
25°C
)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
I
D
I
der
=
-------------------
×
100
%
-
I
D
(
25°C
)
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
001aae811
t
p
= 10
µs
100
µs
10
DC
1 ms
1
1
10
V
DS
(V)
10
2
T
mb
= 25
°C;
I
DM
is single pulse; V
GS
= 10 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD_PHP36N03LT_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 8 June 2006
3 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4.
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Conditions
Min
-
-
[1]
[1]
Symbol Parameter
thermal resistance from junction to ambient
SOT78
SOT428
Typ
-
60
75
50
Max
2.6
-
-
-
Unit
K/W
K/W
K/W
K/W
thermal resistance from junction to mounting base see
Figure 4
vertical in free air
minimum footprint
SOT404 minimum footprint
-
-
[1]
Mounted on a printed-circuit board; vertical in still air.
10
Z
th(j−mb)
(K/W)
δ
= 0.5
1
0.2
0.1
0.05
10
−1
0.02
P
001aae810
δ
=
t
p
T
single pulse
t
p
t
T
10
−2
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD_PHP36N03LT_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 8 June 2006
4 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5.
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown
voltage
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 250
µA;
V
DS
= V
GS
; see
Figure 9
and
10
T
j
= 25
°C
T
j
= 175
°C
T
j
=
−55 °C
I
DSS
drain leakage current
V
DS
= 24 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 175
°C
I
GSS
R
DSon
gate leakage current
drain-source on-state
resistance
V
GS
=
±20
V; V
DS
= 0 V
V
GS
= 4.5 V; I
D
= 12 A; see
Figure 6
and
8
T
j
= 25
°C
T
j
= 175
°C
V
GS
= 10 V; I
D
= 25 A; see
Figure 6
and
8
V
GS
= 3.5 V; I
D
= 5.2 A; see
Figure 6
and
8
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
I
S
= 25 A; V
GS
= 0 V; see
Figure 13
V
DS
= 15 V; R
L
= 0.6
Ω;
V
GS
= 10 V;
R
G
= 10
Ω
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
see
Figure 14
I
D
= 36 A; V
DS
= 15 V; V
GS
= 10 V;
see
Figure 11
and
12
-
-
-
-
-
-
-
-
-
-
-
18.5
4.2
2.9
690
160
110
6
10
33
19
0.97
-
-
-
-
-
-
-
-
-
-
1.2
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
-
-
-
-
18
32.4
14
22
22
39.6
17
40
mΩ
mΩ
mΩ
mΩ
-
-
-
0.05
-
10
1
500
100
µA
µA
nA
1
0.5
-
1.5
-
-
2
-
2.2
V
V
V
30
27
-
-
-
-
V
V
Conditions
Min
Typ
Max
Unit
Source-drain diode
PHD_PHP36N03LT_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 8 June 2006
5 of 13
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