2:2, Differential-to-LVPECL/LVDS Divider
ICS879S216I-02
DATA SHEET
General Description
The ICS879S216I-02 is a Differential-to-LVPECL/ LVDS Clock
Divider which can operate up to 2.5GHz. ICS879S216I-02 has 2
selectable differential clock inputs. The fully differential architecture
and low propagation delay make it ideal for use in clock distribution
circuits. ICS879S216I-02 can divide the input clock by ÷2, ÷4, ÷8
and ÷16. Table 4A lists all the available output dividers.
Features
•
•
•
•
•
•
•
•
•
•
High speed 2:2 differential divider
Two differential LVPECL or LVDS output pairs
Four selectable divide combinations
PCLKx can accept the following input levels: LVPECL, LVDS, CML
Maximum input frequency: 2.5GHz
Propagation delay: 0.8ns (minimum), 1.6ns (maximum)
Output Skew: 25ps (maximum)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 5) package
Table 1A. V
CC_TAP
Function Table
Outputs
Q[1:0], nQ[1:0]
LVPECL
LVPECL
LVDS
LVDS
Output Level Supply
2.5V
3.3V
2.5V
3.3V
V
CC_TAP
V
CC
V
CC
V
CC
Float
Table 1B. SEL_OUT Function Table
Input
SEL_OUT
1
0
Outputs
Q[1:0], nQ[1:0]
LVPECL (default)
LVDS
Block Diagram
SEL_OUT
Pullup
CLK_SEL
Pulldown
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
Pin Assignment
V
EE
CLK_SEL
PCLK0
nPCLK0
1
2
3
4
5
6
24 23 22 21 20 19
18 V
CC
17
nc
nc
0
N
00
01
10
11
1
÷2,
÷4,
÷8,
÷16
(default)
Q0
PCLK1
nPCLK1
nQ0
Q1
SEL_OUT
7
V
CC
8
V
CC_TAP
13 V
EE
9 10 11 12
F_SEL1
F_SEL0
V
EE
nc
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
nQ1
ICS879S216I-02
2
F_SEL[1:0]
Pullup
24-Lead VFQFN
4mm x 4mm x 0.95
mm package body
K Package
Top View
ICS879S216AKI-02 REVISION A APRIL 8, 2011
1
©2011 Integrated Device Technology, Inc.
nQ1
nQ0
Q0
Q1
16 nc
15 nc
14 nc
ICS879S216I-02 Data Sheet
2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
Table 2. Pin Descriptions
Number
1
2
3
4
5
6
7, 18
8
9, 13, 23
10, 14. 15,
16, 17, 24
11,
12
19, 20
21, 22
Name
CLK_SEL
PCLK0
nPCLK0
PCLK1
nPCLK1
SEL_OUT
V
CC
V
CC_TAP
V
EE
nc
F_SEL1,
F_SEL0
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Input
Power
Power
Power
Unused
Input
Output
Output
Pullup
Type
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup
Description
Clock select input. See Table 4B. LVCMOS/LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
Select pin. See Table 1B. LVCMOS/LVTTL interface levels.
Power supply pins.
Power supply pin. See Table 1A.
Negative supply pins.
No connect.
Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 3. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
Ω
k
Ω
Function Tables
Table 4A. Clock Input Function Table
Input
F_SEL1
0
0
1
1
F_SEL0
0
1
0
1
Divide
2
4
8
16 (default)
CLK_SEL
0
1
Table 4B. CLK_SEL Function Table
Inputs
PCLK[0:1], nPCLK[0:1]
PCLK0, nPCLK0 (default)
PCLK1, nPCLK1
NOTE: CLK_SEL is an asynchronous control.
ICS879S216AKI-02 REVISION A APRIL 8, 2011
2
©2011 Integrated Device Technology, Inc.
ICS879S216I-02 Data Sheet
2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
10mA
15mA
49.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 5A. LVPECL Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
65
Units
V
V
mA
Table 5B. LVPECL Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
60
Units
V
V
mA
Table 5C. LVDS Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
CC_TAP
= Float, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
95
Units
V
mA
Table 5D. LVDS Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
90
Units
V
V
mA
ICS879S216AKI-02 REVISION A APRIL 8, 2011
3
©2011 Integrated Device Technology, Inc.
ICS879S216I-02 Data Sheet
2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
Table 5E. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CC_TAP
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
Input Low Voltage
CLK_SEL
I
IH
Input
High Current
F_SEL[1:0],
SEL_OUT
CLK_SEL
I
IL
Input
Low Current
F_SEL[1:0],
SEL_OUT
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
-150
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
10
Units
V
V
V
V
µA
µA
µA
µA
V
IL
Table 5F. LVPECL DC Characteristics,
V
CC
= V
CC_TAP
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input High Current
PCLK0, nPCLK0,
PCLK1, nPCLK1
PCLK0, PCLK1
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Input Low Current
nPCLK0, nPCLK1
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Peak-to-Peak Output Voltage Swing
Test Conditions
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
-10
-150
0.15
V
EE
+ 0.5
V
CC
– 1.4
V
CC
– 2.0
0.6
1.3
V
CC
– 0.85
V
CC
– 0.8
V
CC
– 1.6
1.0
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
NOTE 3: Outputs terminated with 50
Ω
to V
CC
– 2V.
Table 5G. LVDS DC Characteristics,
V
CC
= 3.3V ± 5%, V
CC_TAP
= Float, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
1.125
Minimum
247
Typical
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
Table 5H. LVDS DC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
SEL_OUT = 0
4
1.1
Minimum
247
Typical
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
ICS879S216AKI-02 REVISION A APRIL 8, 2011
©2011 Integrated Device Technology, Inc.
ICS879S216I-02 Data Sheet
2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
AC Electrical Characteristics
Table 6A. LVPECL AC Characteristics,
V
CC
= V
CC_TAP
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
IN
Parameter
Input Frequency
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tp
LH
tsk(i)
tsk(o)
tsk(pp)
t
R
/ t
F
odc
MUX
ISOLATION
Propagation Delay, Low-to-High;
NOTE 1
Input Skew
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 2; 4
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation; NOTE 5
20% to 80%
90
47
>100
0.8
Test Conditions
Minimum
Typical
Maximum
2.5
1.25
625
312.5
156.25
1.6
60
25
650
250
53
Units
GHz
GHz
MHz
MHz
MHz
ns
ps
ps
ps
ps
%
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined according with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output
crossing point.
NOTE 5: Q, nQ outputs measured differentially. See
MUX Isolation diagram
in the Parameter Measurement Information Section.
Table 6B. LVPECL AC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
IN
Parameter
Input Frequency
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tp
LH
tsk(i)
tsk(o)
tsk(pp)
t
R
/ t
F
odc
MUX
ISOLATION
Propagation Delay, Low-to-High;
NOTE 1
Input Skew
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 2; 4
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
20% to 80%
90
47
>100
0.8
Test Conditions
Minimum
Typical
Maximum
2.5
1.25
625
312.5
156.25
1.6
60
25
650
250
53
Units
GHz
GHz
MHz
MHz
MHz
ns
ps
ps
ps
ps
%
dB
For NOTES, see Table 6A above.
ICS879S216AKI-02 REVISION A APRIL 8, 2011
5
©2011 Integrated Device Technology, Inc.
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