SY89871UMG datasheet, PDF - EEWORLD Datasheet

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SY89871U

2.5GHz Any Diff. In-To-LVPECL

Programmable Clock Divider/Fanout Buffer

w/ Internal Termination

General Description

The SY89871U is a 2.5V/3.3V LVPECL output precision

clock divider capable of accepting a high-speed differential

clock input (AC or DC-coupled) CML, LVPECL, HSTL or

LVDS clock input signal and dividing down the frequency

using a programmable divider ratio to create a frequency-

locked lower speed version of the input clock (Bank B).

Available divider ratios are 2, 4, 8, and 16. In a typical

622MHz clock system this would provide availability of

311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock

components.

The differential input buffer has a unique internal

termination design that allows access to the termination

network through a VT pin. This feature allows the device to

easily interface to different logic standards. A V

REF-AC

reference is included for AC-coupled applications.

The SY89871U includes two phase-matched output banks.

Bank A (QA) is a frequency-matched copy of the input.

Bank B (QB0, QB1) is a divided down output of the input

frequency. Bank A and Bank B maintain a matched delay

independent of the divider setting.

Data sheets and support documentation can be found on

Micrel’s web site at:

www.micrel.com.

Precision Edge

®

Features



Two matched-delay outputs:

- Bank A: undivided pass-through (QA)

- Bank B: programmable divide by 2, 4, 8, 16 (QB0,

QB1)



Matched delay: all outputs have matched delay,

independent of divider setting



Guaranteed AC performance:

- >2.5GHz f

MAX

- <250ps t

r

/t

f

- <670ps t

pd

(matched delay)

- <15ps within-device skew



Low jitter design

- 231fs RMS phase jitter (Typ)



Power supply 3.3V or 2.5V



Unique patent-pending input termination and VT pin for

DC- and AC- coupled inputs: any differential inputs

(LVPECL, LVDS, CML, HSTL)



TTL/CMOS inputs for select and reset



100K EP compatible LVPECL outputs



Parallel programming capability



Wide operating temperature range: -40°C to +85°C



Available in 16-pin (3mm x 3mm) QFN package

Typical Performance

Applications



OC-3 to OC-192 SONET/SDH applications

Transponders

Oscillators

SONET/SDH line cards

United States Patent No. RE44,134

Precision Edge is a registered trademark of Micrel, Inc

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (

408

) 944-0800 • fax + 1 (408) 474-1000 •

http://www.micrel.com

Oct. 1, 2013

M9999-010512-F

hbwhelp@micrel.com

or (408) 955-1690

Functional Block Diagram

Ordering Information

Part Number

SY89871UMG

Note:

1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.

2. Tape and Reel.

(2)

(1,2)

Package Type

QFN-16

Operating Range

Industrial

Package Marking

871U with Pb-Free bar line indicator

Lead Finish

NiPdAu Pb-Free

SY89871UMGTR

Oct. 1, 2013

2

M9999-010512-F

hbwhelp@micrel.com

or (408) 955-1690

Micrel, Inc.

SY89871U

Pin Configuration

Pin Description

Pin Number

1, 2, 3, 4

5, 6

7, 14

8

12, 9

10

Pin Name

QB0, /QB0

QB1, /QB1

QA, /QA

VCC

/RESET

IN, /IN

VREF-AC

Pin Function

Differential Buffered Output Clocks: The differential output is a divided-down version of the

input frequency and has a matched output delay with Bank A. Divided by 2, 4, 8, or 16. See

“Truth Table.” Unused output pairs may be left floating.

Differential Buffered Undivided Output Clock.

Positive Power Supply: Bypass with 0.1µF and 0.01µF low ESR capacitors.

Output Reset: Internal 25KΩ pull-up. Logic LOW will reset the divider select. See “Truth Table.”

Input threshold is V

CC

/2.

Differential Input: Internal 50Ω termination resistors to VT input. See “Input Interface

Applications” section.

Reference Voltage: Equal to V

CC

–1.4V (approx.), and used for AC-coupled applications. For

DC-coupled applications, VREF-AC is normally left floating. Maximum sink/source current is

0.5mA. See “Input Interface Applications” section.

Input Termination Center-Tap: Each side of differential input pair terminates to this pin. The VT

pin provides a center tap to a termination network for maximum interface flexibility. For CML

and LVDS inputs, leave this pin floating. See “Input Interface Application” section.

Ground.

Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25KΩ pull-up resistor. Logic

HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is V

CC

/2.

11

13

15, 16

VT

GND

S1, S0

Truth Table

/RESET

1

0

S1

0

1

X

S0

0

1

0

1

X

Bank A Output

Input Clock

Bank B Outputs

Input Clock



2

Input Clock



4

Input Clock



8

Input Clock



16

QB = LOW, /QB = HIGH

Oct. 1, 2013

3

M9999-010512-F

hbwhelp@micrel.com

or (408) 955-1690

Micrel, Inc.

SY89871U

Absolute Maximum Ratings

(1)

Supply Voltage (V

CC

) .................................... –0.5V to +4.0V

Input Voltage (V

IN

) .................................. –0.5V to V

CC

+0.3V

PECL Output Current (I

OUT

)

Continuous. ........................................................... 50mA

Surge .................................................................. 100mA

V

T

Current (I

VT

) ........................................................

100mA

Input Current IN, /IN (I

IN

) ...........................................

50mA

R

REF-AC

Sink/Source Current (I

VREF-AC

) .........................

2mA

Lead Temperature (soldering, 20 sec.) ...................... 260°C

Storage Temperature (T

S

) ........................... –65°C to 150°C

Operating Ratings

(2)

Supply Voltage (V

CC

) .............................. +2.375V to +3.63V

Ambient Temperature (T

A

) .......................... –40°C to +85°C

(3)

Package Thermal Resistance

QFN (

JA

)

Still-Air ............................................................ 60°C/W

500lfpm ........................................................... 54°C/W

QFN (

JB

)

Junction-to-board ........................................... 38°C/W

DC Electrical Characteristics

(4)

T

A

= –40°C to +85°C, unless otherwise stated.

Symbol

V

CC

I

CC

R

IN

V

IH

V

IL

V

IN

V

DIFF_IN

|I

IN

|

V

REF_AC

Notes:

1. Permanent device damage may occur if ratings in the “Absolute Maximum Ratings” sections are exceeded. This is a stress rating only and functional

operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings

conditions for extended periods may affect device reliability.

2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

3. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most Negative potential on the PCB.

4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

5. See “Timing Diagram” for VIN definition. VIN (max.) is specified when VT is floating.

6. See “Typical Operating Characteristics” section for VDIFF definition.

7. Due to the internal termination (see “Input Buffer Structure” section) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not

apply a combination of voltages that causes the input current to exceed the maximum limit.

Parameter

Power Supply Voltage

Power Supply Current

Differential Input Resistance, (IN-to-/IN)

Input HIGH Voltage, (IN-to-/IN)

Input LOW Voltage, (IN-to-/IN)

Input Voltage Swing

Differential Input Voltage Swing

Input Current, (IN-to-/IN)

Reference Voltage

Condition

No load, max V

CC

.

Min

2.37

Typ

50

Max

3.60

75

110

V

CC

+0.3

V

IH

–0.1

V

CC

45

Units

V

mA

Ω

V

mA

V

90

0.1

–0.3

Note 5

Notes 5, 6

Note 7

V

CC

–1.525

0.1

0.2

100

V

CC

–1.425

V

CC

–1.325

Oct. 1, 2013

4

M9999-010512-F

hbwhelp@micrel.com

or (408) 955-1690

Micrel, Inc.

SY89871U

(100KEP) LVPECL DC Electrical Characteristics

(8)

VCC = 3.3V



10% or 2.5V



5%; T

A

= –40°C to +85°C, R

L

= 50Ω to V

CC

–2V, unless otherwise stated.

Symbol

Parameter

Condition

Min

Typ

Max

Units

V

OH

V

OL

V

OUT

V

DIFF_OUT

Output HIGH Voltage

Output LOW Voltage

Output Voltage Swing

Differential Output Voltage Swing

V

CC

–1.145

V

CC

–1.945

550

1.10

V

CC

–1.020

V

CC

–1.820

800

1.6

V

CC

–0.895

V

CC

–1.695

1050

2.1

V

mV

V

LVTTL/ LVCMOS DC Electrical Characteristics

(8)

VCC = 3.3V



10% or 2.5V



5%; T

A

= –40°C to +85°C.

Symbol

Parameter

Condition

V

IH

V

IL

I

IH

I

IL

Input HIGH Voltage

Input LOW Voltage

Input HIGH Current

Input LOW Current

–125

Min

2.0

0.8

20

–300

Typ

Max

Units

V

µA

Note:

8. The circuit is designed to meet the DC specification s shown in the above table after thermal equilibrium has been established. Parameters are for

VCC = 2.5V. They vary 1:1 with VCC.

Oct. 1, 2013

5

M9999-010512-F

hbwhelp@micrel.com

or (408) 955-1690

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	EAR99
Part Status	Active
HTS	8542.39.00.01
Type	Divider Buffer
Fanout	1:1/1:2
Number of Outputs per Chip	6
Maximum Propagation Delay Time @ Maximum CL (ns)	0.71@2.375V to 3.63V
Absolute Propagation Delay Time (ns)	0.71
Input Logic Level	CML\|HSTL\|LVDS\|LVPECL
Output Logic Level	LVPECL
Minimum Operating Supply Voltage (V)	2.375
Typical Operating Supply Voltage (V)	2.5\|3.3
Maximum Operating Supply Voltage (V)	3.63
Maximum Quiescent Current (mA)	75
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	85
Supplier Temperature Grade	Industrial
Packaging	Tube
Pin Count	16
Standard Package Name	QFN
Supplier Package	QFN EP
Mounting	Surface Mount
Package Height	0.85(Max)
Package Length	3
Package Width	3
PCB changed	16
Lead Shape	No Lead

	SY89871UMG	SY89871UMG-TR
Description	Clock Divider Buffer 6-OUT 1-IN 1:1/1:2 16-Pin QFN EP Tube	Clock Divider Buffer 6-OUT 1-IN 1:1/1:2 16-Pin QFN EP T/R
EU restricts the use of certain hazardous substances	Compliant	Compliant
ECCN (US)	EAR99	EAR99
Part Status	Active	Active
HTS	8542.39.00.01	8542.39.00.01
Type	Divider Buffer	Divider Buffer
Fanout	1:1/1:2	1:1/1:2
Number of Outputs per Chip	6	6
Maximum Propagation Delay Time @ Maximum CL (ns)	0.71@2.375V to 3.63V	0.71@2.375V to 3.63V
Absolute Propagation Delay Time (ns)	0.71	0.71
Input Logic Level	CML\|HSTL\|LVDS\|LVPECL	CML\|HSTL\|LVDS\|LVPECL
Output Logic Level	LVPECL	LVPECL
Minimum Operating Supply Voltage (V)	2.375	2.375
Typical Operating Supply Voltage (V)	2.5\|3.3	2.5\|3.3
Maximum Operating Supply Voltage (V)	3.63	3.63
Maximum Quiescent Current (mA)	75	75
Minimum Operating Temperature (°C)	-40	-40
Maximum Operating Temperature (°C)	85	85
Supplier Temperature Grade	Industrial	Industrial
Packaging	Tube	Tape and Reel
Pin Count	16	16
Supplier Package	QFN EP	QFN EP
Mounting	Surface Mount	Surface Mount
Package Height	0.85(Max)	0.85(Max)
Package Length	3	3
Package Width	3	3
PCB changed	16	16

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