GSM Receiver Circuit
PMB 2401
Preliminary Data
Bipolar IC
Features
q
Heterodyne receiver with demodulator
q
Down mixing from 900 MHz receiver band to the base
q
q
q
q
q
q
q
q
q
q
q
q
band
Demodulation and generation of I/Q-baseband
components
Low mixer noise 10 dB (SSB)
Input high intercept point + 2 dB
Integrated 0˚ and 90˚ phase shifter
82 dB AGC-range
On-chip second LO-oscillator with external tuning circuit
Two differential operational amplifiers
Low power consumption due to highly flexible power-
down capability
Wide input frequency range up to 1 GHz
Wide IF-range from 35 MHz to 100 MHz
P-DSO-28 package and P-DSO-28-4 shrink package
Temperature range – 25 ˚C to 85 ˚C
P-DSO-28
P-DSO-28-4
Applications
q
Digital mobile cellular systems as GSM, DAMPS, JDC
q
Various demodulation schemes, such as PM, PSK, FSK, QAM, QPSK, GMSK
q
Space and power saving optimizations of existing discrete demodulator circuits
Type
PMB 2401T
PMB 2401T
PMB 2401S
PMB 2401S
Version
V 2.1
V 2.1
V 2.1
V 2.1
Ordering Code
Q67000-A6061
Q67006-A6061
Q67000-A6062
Q67006-A6062
Package
P-DSO-28 (SMD)
P-DSO-28
(SMD, Tape + Reel)
P-DSO-28-4
(Shrink, SMD)
P-DSO-28-4 (Shrink,
SMD, Tape + Reel)
Semiconductor Group
1
01.94
PMB 2401
Functional Description
The PMB 2401 is a single-chip single-conversion heterodyn PM-receiver with phase shifting
circuitry for the I/Q-phase baseband demodulation on chip. It also includes the second local
oscillator, a gain controlled second IF-amplifier, two differential operational amplifiers for baseband
filtering purposes and power down circuitry.
The PMB 2401 is designed for digital mobile telephones according to the GSM-standard and other
digital systems.
Pin Configuration
(top view)
Semiconductor Group
2
PMB 2401
Pin Definitions and Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
SOI
SOQ
INQ
OUTQ
OUTQ
INQ
SOQ
LO2E
LO2B
GND
IFI
IFI
GC
LO2O
MO
MO
Function
Non-inverting in-phase signal output
Non-inverting quadratur signal output
Inverting op. amp. signal output (Q)
Non-inverting op. amp. signal output (Q)
Inverting op. amp. signal output (Q)
Non-inverting op. amp. signal input (Q)
Inverting quadratur signal output
External capacitors for oscillator
VCO-tuning circuit
Ground
Inverting IF input
Non-inverting IF input
Gain control input
VCO-signal output
Inverted output of first mixer
Non-inverted output of first mixer
Supply voltage
Non-inverted signal input of first mixer
Inverted signal input of first mixer
Power-down input 1
Non-inverting input for first local oscillator
Inverting input for first local oscillator
Power-down input 2
Inverting in-phase signal output
Non-inverting op. amp. signal input (I)
Inverting op. amp. signal output (I)
Non-inverting op. amp. signal output (I)
Inverting op. amp. signal input (I)
V
S
SI
SI
PD1
LO1
LO1
PD2
SOI
INI
OUTI
OUTI
INI
Semiconductor Group
3
PMB 2401
Block Diagram
Semiconductor Group
4
PMB 2401
Circuit Description
The input signal SI/SI and the amplified first local oscillator signal LO1/LO1 are mixed down to an
intermediate frequency (IF). The open collector output of the mixer generates a differential current
at pins MO/MO which is filtered by an external resonant circuit. The resulting voltage drives an
external SAW-filter.
The second local oscillator signal LO2 is generated in an on chip VCO and is fed to two dividers,
which generate orthogonal signals at a quarter of VCO-frequency. The internal LO-signal is fed to
an additionally divider, whose output signal LO2O is fed to the RF-signal of PLL-synthesizer. The
filtered IF-signal reenters the chip at the IFI/IFI input, where it is amplified and demodulated to the
final baseband output frequency with each of the orthogonal signals. The resulting in-phase and
quadrature signals pass through differential output drivers and appear at SOI/SOI and SOQ/SOQ
outputs, respectively. The amplification of the IF-signal before the second mixer stage is performed
by a gain-controlled amplifier, the gain being determined by the voltage at the gain control input GC.
Two differential operational amplifiers with the input signals INI/INI (INQ/INQ) and the output signals
OUTI/OUTI (OUTQ/OUTQ) can be used as active filters.
Differential signals and symmetrical circuitry are used throughout, except at the signal output. Bias
drivers generate internal temperature- and supply voltage-compensated reference voltages
required by various circuit blocks. Switching the power down inputs PD1 and PD2 from high to low
(see
table)
sets the circuit from its normal operating mode into a mode with reduced supply current.
PD1
L
L
H
H
PD2
L
H
L
H
RF-Part
OFF
OFF
ON
ON
IF-Part
OFF
ON
OFF
ON
VCO/Divders
ON
ON
ON
ON
Semiconductor Group
5
Analog electronics
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