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74LVC823ABQ115

Description
Flip Flops 9BIT BUS INTERFACE REG 3-ST
Categorysemiconductor    logic   
File Size799KB,21 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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74LVC823ABQ115 Overview

Flip Flops 9BIT BUS INTERFACE REG 3-ST

74LVC823ABQ115 Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerNXP
Product CategoryFlip Flops
Number of Circuits1
Logic FamilyLVC
Logic TypeD-Type Edge Triggered Flip-Flop
PolarityNon-Inverting
Input TypeSingle-Ended
Propagation Delay Time5.4 ns at 3.3 V
High Level Output Current- 24 mA
Supply Voltage - Min1.2 V
Supply Voltage - Max3.6 V
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 125 C
Mounting StyleSMD/SMT
Package / CaseSOT-815
PackagingReel
Height0.95 mm
Length5.6 mm
Quiescent Current100 uA
Width3.6 mm
Number of Input Lines9
Number of Output Lines9
Operating Supply Voltage1.8 V, 2.5 V, 3.3 V
Reset TypeMaster Reset
Factory Pack Quantity3000
74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive
edge-trigger; 3-state
Rev. 4 — 8 April 2013
Product data sheet
1. General description
The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable
(pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented
applications. The 9 flip-flops stores the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW to HIGH CP transition, provided pin CE is
LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all
flip-flops. When pin OE is LOW, the contents of the 9 flip-flops are available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pinout architecture
9-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C.
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